diff mbox series

riscv/sifive_u: fix a memory leak in soc_realize()

Message ID 1575962077-28800-1-git-send-email-pannengyuan@huawei.com
State New
Headers show
Series riscv/sifive_u: fix a memory leak in soc_realize() | expand

Commit Message

Pan Nengyuan Dec. 10, 2019, 7:14 a.m. UTC 
From: Pan Nengyuan <pannengyuan@huawei.com>

Fix a minor memory leak in riscv_sifive_u_soc_realize()

Reported-by: Euler Robot <euler.robot@huawei.com>
Signed-off-by: Pan Nengyuan <pannengyuan@huawei.com>
---
 hw/riscv/sifive_u.c | 1 +
 1 file changed, 1 insertion(+)

Comments

Philippe Mathieu-Daudé Dec. 10, 2019, 7:46 a.m. UTC | #1 
On 12/10/19 8:14 AM, pannengyuan@huawei.com wrote:
> From: Pan Nengyuan <pannengyuan@huawei.com>
> 
> Fix a minor memory leak in riscv_sifive_u_soc_realize()
> 
> Reported-by: Euler Robot <euler.robot@huawei.com>
> Signed-off-by: Pan Nengyuan <pannengyuan@huawei.com>
> ---
>   hw/riscv/sifive_u.c | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 0140e95..0e12b3c 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -542,6 +542,7 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
>           SIFIVE_U_PLIC_CONTEXT_BASE,
>           SIFIVE_U_PLIC_CONTEXT_STRIDE,
>           memmap[SIFIVE_U_PLIC].size);
> +    g_free(plic_hart_config);
>       sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base,
>           serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
>       sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base,
> 

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Alistair Francis Dec. 10, 2019, 6:38 p.m. UTC | #2 
On Mon, Dec 9, 2019 at 11:15 PM <pannengyuan@huawei.com> wrote:
>
> From: Pan Nengyuan <pannengyuan@huawei.com>
>
> Fix a minor memory leak in riscv_sifive_u_soc_realize()
>
> Reported-by: Euler Robot <euler.robot@huawei.com>
> Signed-off-by: Pan Nengyuan <pannengyuan@huawei.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  hw/riscv/sifive_u.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 0140e95..0e12b3c 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -542,6 +542,7 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
>          SIFIVE_U_PLIC_CONTEXT_BASE,
>          SIFIVE_U_PLIC_CONTEXT_STRIDE,
>          memmap[SIFIVE_U_PLIC].size);
> +    g_free(plic_hart_config);
>      sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base,
>          serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
>      sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base,
> --
> 2.7.2.windows.1
>
>
>
Palmer Dabbelt Jan. 9, 2020, 11:42 p.m. UTC | #3 
On Tue, 10 Dec 2019 10:38:29 PST (-0800), alistair23@gmail.com wrote:
> On Mon, Dec 9, 2019 at 11:15 PM <pannengyuan@huawei.com> wrote:
>>
>> From: Pan Nengyuan <pannengyuan@huawei.com>
>>
>> Fix a minor memory leak in riscv_sifive_u_soc_realize()
>>
>> Reported-by: Euler Robot <euler.robot@huawei.com>
>> Signed-off-by: Pan Nengyuan <pannengyuan@huawei.com>
>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Thanks.  This is in the queue, I'm hoping to submit a PR after the H patch set
is ready to go.

>
> Alistair
>
>> ---
>>  hw/riscv/sifive_u.c | 1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
>> index 0140e95..0e12b3c 100644
>> --- a/hw/riscv/sifive_u.c
>> +++ b/hw/riscv/sifive_u.c
>> @@ -542,6 +542,7 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
>>          SIFIVE_U_PLIC_CONTEXT_BASE,
>>          SIFIVE_U_PLIC_CONTEXT_STRIDE,
>>          memmap[SIFIVE_U_PLIC].size);
>> +    g_free(plic_hart_config);
>>      sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base,
>>          serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
>>      sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base,
>> --
>> 2.7.2.windows.1
>>
>>
>>
diff mbox series

Patch

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 0140e95..0e12b3c 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -542,6 +542,7 @@  static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
         SIFIVE_U_PLIC_CONTEXT_BASE,
         SIFIVE_U_PLIC_CONTEXT_STRIDE,
         memmap[SIFIVE_U_PLIC].size);
+    g_free(plic_hart_config);
     sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base,
         serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
     sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base,