[v1,33/36] target/riscv: Set htval and mtval2 on execptions

Message ID	3d0d12048c2cf4c5c5ec888b9ff602620285fa5b.1575914822.git.alistair.francis@wdc.com
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> IronPort-SDR: xGB7mZAytnZEeKXw6cHpYGoEnjSnRkqx+DHA5ih5eeRGQmMhTtJMgmMJOoTIdwKh7/WF627mAG M0hTuMVOmWmk97f5nEG5XFzyflTgoe1ew53NUjcJ7Ape9IKZB8tPuW97RVRfrjfI4IKAZF9ciV ADEdY0xPHUUY9+AmuBJI56mGDJWxcx0iVKneOj0druakKWldvip8MT6txuGK/IWq04klHHXJuN j30Pt5Gh6adLlqXVEpLwSKgPLxD+deJq5SBF9gnLRMKXYJGg1MX8rK71mXgNMtqvQHETIAX14r BDY= IronPort-SDR: sbC0hzYTtLMk2gtPKiD6vcCsm+LVd1dW0wm6NArMpXAt/KXesuCJxO85sP3uAkjSr0P9xpWu8M F0gkmrYeOD1TeH/j1zL3a8wymMNHpvYeoy2YnlHBZXVMKp3PopQ7WTJ1VZlc7CJQGLWneyWTTS Jqc5J90ASGMQFhiOv6A82soEqWn+L3u0xjN9fo5eKXk5E0mrpHuTFGkemYl/S6YXDRuPAq74HQ bw70LGVH09Ut+iewoWb0fxan7RQ5Kt3OXrRtHZ6t/qTskaO8iAOUjKVOn5rnKg6hHCvvLL8xtq daPSKN6RKbQ+1pK7T/q+MBDb IronPort-SDR: PNvQLqM1PWSRLkhXMV1HGSFPCYC3oO4UtiHLvfA3cTVpgEBbY/ytHFR+sy2/UykeqNIXBdyqpz kADx6ODh2eHuMpz81tGy4xeOjERIHhjRBo7oUjAfTFiolbrgRS/PsVY83fxYA4kZiZEuX9JeLj I8IOhXXKvLv3l047gdLtkwMQmQWLMBIIEoWTuXk+FLDzb/mnDVMURD+eTfXN+78EDIQBDKQhYX DVKrCubv4VINWYPrgJro7ygv4axTaU580hVsu7S6yskFmzSE2Z4d6Jr/1rAcc2I2qrhsWwFw+h G8Q= WDCIronportException: Internal From: Alistair Francis <alistair.francis@wdc.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v1 33/36] target/riscv: Set htval and mtval2 on execptions Date: Mon, 9 Dec 2019 10:12:06 -0800 Message-Id: <3d0d12048c2cf4c5c5ec888b9ff602620285fa5b.1575914822.git.alistair.francis@wdc.com> In-Reply-To: <cover.1575914822.git.alistair.francis@wdc.com> References: <cover.1575914822.git.alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: list Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	Add RISC-V Hypervisor Extension v0.5 \| expand [v1,00/36] Add RISC-V Hypervisor Extension v0.5 [v1,01/36] target/riscv: Convert MIP CSR to target_ulong [v1,02/36] target/riscv: Don't set write permissions on dirty PTEs [v1,03/36] target/riscv: Add the Hypervisor extension [v1,04/36] target/riscv: Add the Hypervisor CSRs to CPUState [v1,05/36] target/riscv: Add support for the new execption numbers [v1,06/36] target/riscv: Rename the H irqs to VS irqs [v1,07/36] target/riscv: Add the virtulisation mode [v1,08/36] target/riscv: Add the force HS exception mode [v1,09/36] target/riscv: Fix CSR perm checking for HS mode [v1,10/36] target/riscv: Print priv and virt in disas log [v1,11/36] target/riscv: Dump Hypervisor registers if enabled [v1,12/36] target/riscv: Add Hypervisor CSR access functions [v1,13/36] target/riscv: Add Hypervisor virtual CSRs accesses [v1,14/36] target/riscv: Add Hypervisor virtual CSRs accesses [v1,15/36] target/riscv: Convert mstatus to pointers [v1,16/36] target/riscv: Add virtual register swapping function [v1,17/36] target/riscv: Set VS bits in mideleg for Hyp extension [v1,18/36] target/riscv: Extend the MIE CSR to support virtulisation [v1,19/36] target/riscv: Extend the SIP CSR to support virtulisation [v1,20/36] target/riscv: Add support for virtual interrupt setting [v1,21/36] target/ricsv: Flush the TLB on virtulisation mode changes [v1,22/36] target/riscv: Generate illegal instruction on WFI when V=1 [v1,23/36] target/riscv: Add hypvervisor trap support [v1,24/36] target/riscv: Add Hypervisor trap return support [v1,25/36] target/riscv: Add hfence instructions [v1,26/36] target/riscv: Remove the hret instruction [v1,27/36] target/riscv: Disable guest FP support based on virtual status [v1,28/36] target/riscv: Mark both sstatus and vsstatus as dirty [v1,29/36] target/riscv: Respect MPRV and SPRV for floating point ops [v1,30/36] target/riscv: Allow specifying MMU stage [v1,31/36] target/riscv: Implement second stage MMU [v1,32/36] target/riscv: Raise the new execptions when 2nd stage translation fails [v1,33/36] target/riscv: Set htval and mtval2 on execptions [v1,34/36] target/riscv: Add support for the 32-bit MSTATUSH CSR [v1,35/36] target/riscv: Add the MSTATUS_MPV_ISSET helper macro [v1,36/36] target/riscv: Allow enabling the Hypervisor extension

Message ID

3d0d12048c2cf4c5c5ec888b9ff602620285fa5b.1575914822.git.alistair.francis@wdc.com

State

New

Headers

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	BDY=
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WDCIronportException: Internal
From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org,
	qemu-riscv@nongnu.org
Subject: [PATCH v1 33/36] target/riscv: Set htval and mtval2 on execptions
Date: Mon,  9 Dec 2019 10:12:06 -0800
Message-Id: <3d0d12048c2cf4c5c5ec888b9ff602620285fa5b.1575914822.git.alistair.francis@wdc.com>
In-Reply-To: <cover.1575914822.git.alistair.francis@wdc.com>
References: <cover.1575914822.git.alistair.francis@wdc.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Precedence: list
Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com
Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org
Sender: "Qemu-devel"
	<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>

Series

Add RISC-V Hypervisor Extension v0.5 | expand

Comments

Palmer Dabbelt Jan. 9, 2020, 2:29 a.m. UTC | #1

On Mon, 09 Dec 2019 10:12:06 PST (-0800), Alistair Francis wrote:
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>  target/riscv/cpu_helper.c | 10 ++++++++++
>  1 file changed, 10 insertions(+)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 43c6629014..aa033b8590 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -841,6 +841,8 @@ void riscv_cpu_do_interrupt(CPUState *cs)
>      target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK;
>      target_ulong deleg = async ? env->mideleg : env->medeleg;
>      target_ulong tval = 0;
> +    target_ulong htval = 0;
> +    target_ulong mtval2 = 0;
>
>      if (!async) {
>          /* set tval to badaddr for traps with address information */
> @@ -900,6 +902,8 @@ void riscv_cpu_do_interrupt(CPUState *cs)
>                  env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
>                                           riscv_cpu_virt_enabled(env));
>
> +                htval = env->guest_phys_fault_addr;
> +
>                  riscv_cpu_set_virt_enabled(env, 0);
>                  riscv_cpu_set_force_hs_excep(env, 0);
>              } else {
> @@ -910,6 +914,8 @@ void riscv_cpu_do_interrupt(CPUState *cs)
>                                           get_field(*env->mstatus, SSTATUS_SPP));
>                  env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
>                                           riscv_cpu_virt_enabled(env));
> +
> +                htval = env->guest_phys_fault_addr;
>              }
>          }
>
> @@ -922,6 +928,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
>          env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1));
>          env->sepc = env->pc;
>          env->sbadaddr = tval;
> +        env->htval = htval;
>          env->pc = (env->stvec >> 2 << 2) +
>              ((async && (env->stvec & 3) == 1) ? cause * 4 : 0);
>          riscv_cpu_set_mode(env, PRV_S);
> @@ -936,6 +943,8 @@ void riscv_cpu_do_interrupt(CPUState *cs)
>              *env->mstatus = set_field(*env->mstatus, MSTATUS_MTL,
>                                        riscv_cpu_force_hs_excep_enabled(env));
>
> +            mtval2 = env->guest_phys_fault_addr;
> +
>              /* Trapping to M mode, virt is disabled */
>              riscv_cpu_set_virt_enabled(env, 0);
>          }
> @@ -949,6 +958,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
>          env->mcause = cause | ~(((target_ulong)-1) >> async);
>          env->mepc = env->pc;
>          env->mbadaddr = tval;
> +        env->mtval2 = mtval2;
>          env->pc = (env->mtvec >> 2 << 2) +
>              ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0);
>          riscv_cpu_set_mode(env, PRV_M);

Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 43c6629014..aa033b8590 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -841,6 +841,8 @@  void riscv_cpu_do_interrupt(CPUState *cs)
     target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK;
     target_ulong deleg = async ? env->mideleg : env->medeleg;
     target_ulong tval = 0;
+    target_ulong htval = 0;
+    target_ulong mtval2 = 0;
 
     if (!async) {
         /* set tval to badaddr for traps with address information */
@@ -900,6 +902,8 @@  void riscv_cpu_do_interrupt(CPUState *cs)
                 env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
                                          riscv_cpu_virt_enabled(env));
 
+                htval = env->guest_phys_fault_addr;
+
                 riscv_cpu_set_virt_enabled(env, 0);
                 riscv_cpu_set_force_hs_excep(env, 0);
             } else {
@@ -910,6 +914,8 @@  void riscv_cpu_do_interrupt(CPUState *cs)
                                          get_field(*env->mstatus, SSTATUS_SPP));
                 env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
                                          riscv_cpu_virt_enabled(env));
+
+                htval = env->guest_phys_fault_addr;
             }
         }
 
@@ -922,6 +928,7 @@  void riscv_cpu_do_interrupt(CPUState *cs)
         env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1));
         env->sepc = env->pc;
         env->sbadaddr = tval;
+        env->htval = htval;
         env->pc = (env->stvec >> 2 << 2) +
             ((async && (env->stvec & 3) == 1) ? cause * 4 : 0);
         riscv_cpu_set_mode(env, PRV_S);
@@ -936,6 +943,8 @@  void riscv_cpu_do_interrupt(CPUState *cs)
             *env->mstatus = set_field(*env->mstatus, MSTATUS_MTL,
                                       riscv_cpu_force_hs_excep_enabled(env));
 
+            mtval2 = env->guest_phys_fault_addr;
+
             /* Trapping to M mode, virt is disabled */
             riscv_cpu_set_virt_enabled(env, 0);
         }
@@ -949,6 +958,7 @@  void riscv_cpu_do_interrupt(CPUState *cs)
         env->mcause = cause | ~(((target_ulong)-1) >> async);
         env->mepc = env->pc;
         env->mbadaddr = tval;
+        env->mtval2 = mtval2;
         env->pc = (env->mtvec >> 2 << 2) +
             ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0);
         riscv_cpu_set_mode(env, PRV_M);

[v1,33/36] target/riscv: Set htval and mtval2 on execptions

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