[v1,01/36] target/riscv: Convert MIP CSR to target_ulong

Message ID	aa8557d53c1f6d3265e2b2c9bc4e127eddb995ea.1575914822.git.alistair.francis@wdc.com
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> IronPort-SDR: GvkjpfjA42fzO/IMzrXJKCIKj/AuDU2gYaZpcthUPMR0Om7bQeC/hc9K9swnhdntwSbgBKHBB0 yoFquwtOLXkuWaNgselpNonG0ShUlzXdtfMDu3H2YK6k4gTsjOEij/9pwxwTc5wJkX4+28LLly gdtmWymcuTbzdajHlo3m9A5C9WKR/ZMXfg+WDumiQ19iQ9D/sGzyEQR3wkMo9bg2/YWctLymg9 B2oW/Dxp7rphA8Fl8h0B2djsuDOwASExRMWkxgDzDjPLMY95dwPNxkTDj5xAeEAu3ajIfDaV+c DqI= IronPort-SDR: /ksCScIUzaOpEdCPJX1Z2rvp20Pt09Uc5NrAyYABMRQw3LrNRLn1cAX32cZSpqNPOhNcLD+U0A Udh3zWMYvhGPFE9M3WDk5ydGoeY3AJ5Ntxq9RZpVu4t7ivXVQzxC5onfDZQ6T0byH1assP86Qe c17ZxFlspVWFhf/0J6e7eofvA8gAvGkBlFxTCeudYRPzaYlMZw5O0O/Q5rZH15HJZ+labK8hEu dFWFkcHpBAbKDVTHLObpDcYbwsd+80P+rK3hK/n/fcxi/BurZ3bIneL0Pd1iPgAJ6Ajb97NTqJ AA2w8/EphSalj7vBqnfEclDR IronPort-SDR: 4nq7+TJHNO/s9ZdE38Gi2P//me/LcmH91d3R5Yo96/UNQHvM7J5W5b+MOfCTaEA/9ZXYxA5bhD xStIox1Ocps/pX2kp9DduGtwOC/UcQsiWux0jP+E4ks4EbX0JtOnPuFE+5MiaXsAiXxZBYTnSZ ZDvB0D/zdtdBceJ1CnMkrQhGKToPzrK3N8CRUrf++yIn9reiGAAE0Phcf4duHM7UUQZIERuFP6 i9PZGJ88N8l3QVLmbBCTLObRJFgpAxzlABIr+TB52hMrnonPmk1Ri4xdVt3Z8rhR0Oeinm8hEG 2u8= WDCIronportException: Internal From: Alistair Francis <alistair.francis@wdc.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v1 01/36] target/riscv: Convert MIP CSR to target_ulong Date: Mon, 9 Dec 2019 10:10:43 -0800 Message-Id: <aa8557d53c1f6d3265e2b2c9bc4e127eddb995ea.1575914822.git.alistair.francis@wdc.com> In-Reply-To: <cover.1575914822.git.alistair.francis@wdc.com> References: <cover.1575914822.git.alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: list Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	Add RISC-V Hypervisor Extension v0.5 \| expand [v1,00/36] Add RISC-V Hypervisor Extension v0.5 [v1,01/36] target/riscv: Convert MIP CSR to target_ulong [v1,02/36] target/riscv: Don't set write permissions on dirty PTEs [v1,03/36] target/riscv: Add the Hypervisor extension [v1,04/36] target/riscv: Add the Hypervisor CSRs to CPUState [v1,05/36] target/riscv: Add support for the new execption numbers [v1,06/36] target/riscv: Rename the H irqs to VS irqs [v1,07/36] target/riscv: Add the virtulisation mode [v1,08/36] target/riscv: Add the force HS exception mode [v1,09/36] target/riscv: Fix CSR perm checking for HS mode [v1,10/36] target/riscv: Print priv and virt in disas log [v1,11/36] target/riscv: Dump Hypervisor registers if enabled [v1,12/36] target/riscv: Add Hypervisor CSR access functions [v1,13/36] target/riscv: Add Hypervisor virtual CSRs accesses [v1,14/36] target/riscv: Add Hypervisor virtual CSRs accesses [v1,15/36] target/riscv: Convert mstatus to pointers [v1,16/36] target/riscv: Add virtual register swapping function [v1,17/36] target/riscv: Set VS bits in mideleg for Hyp extension [v1,18/36] target/riscv: Extend the MIE CSR to support virtulisation [v1,19/36] target/riscv: Extend the SIP CSR to support virtulisation [v1,20/36] target/riscv: Add support for virtual interrupt setting [v1,21/36] target/ricsv: Flush the TLB on virtulisation mode changes [v1,22/36] target/riscv: Generate illegal instruction on WFI when V=1 [v1,23/36] target/riscv: Add hypvervisor trap support [v1,24/36] target/riscv: Add Hypervisor trap return support [v1,25/36] target/riscv: Add hfence instructions [v1,26/36] target/riscv: Remove the hret instruction [v1,27/36] target/riscv: Disable guest FP support based on virtual status [v1,28/36] target/riscv: Mark both sstatus and vsstatus as dirty [v1,29/36] target/riscv: Respect MPRV and SPRV for floating point ops [v1,30/36] target/riscv: Allow specifying MMU stage [v1,31/36] target/riscv: Implement second stage MMU [v1,32/36] target/riscv: Raise the new execptions when 2nd stage translation fails [v1,33/36] target/riscv: Set htval and mtval2 on execptions [v1,34/36] target/riscv: Add support for the 32-bit MSTATUSH CSR [v1,35/36] target/riscv: Add the MSTATUS_MPV_ISSET helper macro [v1,36/36] target/riscv: Allow enabling the Hypervisor extension

Message ID

aa8557d53c1f6d3265e2b2c9bc4e127eddb995ea.1575914822.git.alistair.francis@wdc.com

State

New

Headers

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WDCIronportException: Internal
From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org,
	qemu-riscv@nongnu.org
Subject: [PATCH v1 01/36] target/riscv: Convert MIP CSR to target_ulong
Date: Mon,  9 Dec 2019 10:10:43 -0800
Message-Id: <aa8557d53c1f6d3265e2b2c9bc4e127eddb995ea.1575914822.git.alistair.francis@wdc.com>
In-Reply-To: <cover.1575914822.git.alistair.francis@wdc.com>
References: <cover.1575914822.git.alistair.francis@wdc.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Precedence: list
Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com
Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org
Sender: "Qemu-devel"
	<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>

Series

Add RISC-V Hypervisor Extension v0.5 | expand

Commit Message

Alistair Francis Dec. 9, 2019, 6:10 p.m. UTC

The MIP CSR is a xlen CSR, it was only 32-bits to allow atomic access.
Now that we don't use atomics for MIP we can change this back to a xlen
CSR.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 2 +-
 target/riscv/cpu.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

Comments

Palmer Dabbelt Jan. 2, 2020, 6:18 p.m. UTC | #1

On Mon, 09 Dec 2019 10:10:43 PST (-0800), Alistair Francis wrote:
> The MIP CSR is a xlen CSR, it was only 32-bits to allow atomic access.
> Now that we don't use atomics for MIP we can change this back to a xlen
> CSR.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>  target/riscv/cpu.c | 2 +-
>  target/riscv/cpu.h | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index d37861a430..e521ebe2e1 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -224,7 +224,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
>  #ifndef CONFIG_USER_ONLY
>      qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
>      qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus);
> -    qemu_fprintf(f, " %s 0x%x\n", "mip     ", env->mip);
> +    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip     ", env->mip);
>      qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie     ", env->mie);
>      qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg);
>      qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg);
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index e59343e13c..f889427869 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -121,7 +121,7 @@ struct CPURISCVState {
>      target_ulong mhartid;
>      target_ulong mstatus;
>
> -    uint32_t mip;
> +    target_ulong mip;
>      uint32_t miclaim;
>
>      target_ulong mie;

Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>

Alistair Francis Jan. 3, 2020, 2:08 a.m. UTC | #2

On Thu, Jan 2, 2020 at 10:18 AM Palmer Dabbelt <palmerdabbelt@google.com> wrote:
>
> On Mon, 09 Dec 2019 10:10:43 PST (-0800), Alistair Francis wrote:
> > The MIP CSR is a xlen CSR, it was only 32-bits to allow atomic access.
> > Now that we don't use atomics for MIP we can change this back to a xlen
> > CSR.
> >
> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > ---
> >  target/riscv/cpu.c | 2 +-
> >  target/riscv/cpu.h | 2 +-
> >  2 files changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index d37861a430..e521ebe2e1 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -224,7 +224,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
> >  #ifndef CONFIG_USER_ONLY
> >      qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
> >      qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus);
> > -    qemu_fprintf(f, " %s 0x%x\n", "mip     ", env->mip);
> > +    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip     ", env->mip);
> >      qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie     ", env->mie);
> >      qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg);
> >      qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg);
> > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> > index e59343e13c..f889427869 100644
> > --- a/target/riscv/cpu.h
> > +++ b/target/riscv/cpu.h
> > @@ -121,7 +121,7 @@ struct CPURISCVState {
> >      target_ulong mhartid;
> >      target_ulong mstatus;
> >
> > -    uint32_t mip;
> > +    target_ulong mip;
> >      uint32_t miclaim;
> >
> >      target_ulong mie;
>
> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>

Thanks!

Can you just apply the patches from this series as they are reviewed?

Also, can you review this series :)

Alistair

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d37861a430..e521ebe2e1 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -224,7 +224,7 @@  static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 #ifndef CONFIG_USER_ONLY
     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus);
-    qemu_fprintf(f, " %s 0x%x\n", "mip     ", env->mip);
+    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip     ", env->mip);
     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie     ", env->mie);
     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg);
     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg);
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index e59343e13c..f889427869 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -121,7 +121,7 @@  struct CPURISCVState {
     target_ulong mhartid;
     target_ulong mstatus;
 
-    uint32_t mip;
+    target_ulong mip;
     uint32_t miclaim;
 
     target_ulong mie;

[v1,01/36] target/riscv: Convert MIP CSR to target_ulong

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