| Message ID | 20191216193825.1794153-4-ehabkost@redhat.com |
|---|---|
| State | New |
| Headers | show |
| Series | [PULL,1/4] i386: Add MSR feature bit for MDS-NO | expand |
On 12/17/2019 3:38 AM, Eduardo Habkost wrote: > From: Cathy Zhang <cathy.zhang@intel.com> > > Cooper Lake is intel's successor to Cascade Lake, the new > CPU model inherits features from Cascadelake-Server, while > add one platform associated new feature: AVX512_BF16. Meanwhile, > add STIBP for speculative execution. > > Signed-off-by: Cathy Zhang <cathy.zhang@intel.com> > Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> > Reviewed-by: Tao Xu <tao3.xu@intel.com> > Message-Id: <1571729728-23284-4-git-send-email-cathy.zhang@intel.com> > Reviewed-by: Bruce Rogers <brogers@suse.com> > Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> > --- > target/i386/cpu.c | 60 +++++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 60 insertions(+) > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index 69f518a21a..de828e29d8 100644 > --- a/target/i386/cpu.c > +++ b/target/i386/cpu.c > @@ -3159,6 +3159,66 @@ static X86CPUDefinition builtin_x86_defs[] = { > { /* end of list */ } > } > }, > + { > + .name = "Cooperlake", > + .level = 0xd, > + .vendor = CPUID_VENDOR_INTEL, > + .family = 6, > + .model = 85, > + .stepping = 10, > + .features[FEAT_1_EDX] = > + CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | > + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | > + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | > + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | > + CPUID_DE | CPUID_FP87, > + .features[FEAT_1_ECX] = > + CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | > + CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | > + CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | > + CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | > + CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | > + CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, > + .features[FEAT_8000_0001_EDX] = > + CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | > + CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, > + .features[FEAT_8000_0001_ECX] = > + CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, > + .features[FEAT_7_0_EBX] = > + CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | > + CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | > + CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | > + CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | > + CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | > + CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | > + CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | > + CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, > + .features[FEAT_7_0_ECX] = > + CPUID_7_0_ECX_PKU | > + CPUID_7_0_ECX_AVX512VNNI, > + .features[FEAT_7_0_EDX] = > + CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP | > + CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES, > + .features[FEAT_ARCH_CAPABILITIES] = > + MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | > + MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO, > + .features[FEAT_7_1_EAX] = > + CPUID_7_1_EAX_AVX512_BF16, > + /* > + * Missing: XSAVES (not supported by some Linux versions, > + * including v4.1 to v4.12). > + * KVM doesn't yet expose any XSAVES state save component, > + * and the only one defined in Skylake (processor tracing) > + * probably will block migration anyway. > + */ > + .features[FEAT_XSAVE] = > + CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | > + CPUID_XSAVE_XGETBV1, > + .features[FEAT_6_EAX] = > + CPUID_6_EAX_ARAT, > + .xlevel = 0x80000008, > + .model_id = "Intel Xeon Processor (Cooperlake)", > + }, > { > .name = "Icelake-Client", > .level = 0xd, > Hi Eduardo, Since this CPU model has been hold for a while, it misses the VMX features added by Paolo recently. Besides, there are two bits PSCHANGE_MC_NO(bit 6) and TAA_NO(bit 8) of MSR_IA32_ARCH_CAPABILITIES disclosed recently, that are also missed in this CPU model. Should we hold off this and update a new patch with the above features added? Or we make this merged and send a new patch to add a new version for the above?
On 12/17/19 3:26 AM, Xiaoyao Li wrote: > On 12/17/2019 3:38 AM, Eduardo Habkost wrote: >> From: Cathy Zhang <cathy.zhang@intel.com> >> >> Cooper Lake is intel's successor to Cascade Lake, the new >> CPU model inherits features from Cascadelake-Server, while >> add one platform associated new feature: AVX512_BF16. Meanwhile, >> add STIBP for speculative execution. >> >> Signed-off-by: Cathy Zhang <cathy.zhang@intel.com> >> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> >> Reviewed-by: Tao Xu <tao3.xu@intel.com> >> Message-Id: <1571729728-23284-4-git-send-email-cathy.zhang@intel.com> >> Reviewed-by: Bruce Rogers <brogers@suse.com> >> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> >> --- >> target/i386/cpu.c | 60 +++++++++++++++++++++++++++++++++++++++++++++++ >> 1 file changed, 60 insertions(+) >> >> diff --git a/target/i386/cpu.c b/target/i386/cpu.c >> index 69f518a21a..de828e29d8 100644 >> --- a/target/i386/cpu.c >> +++ b/target/i386/cpu.c >> @@ -3159,6 +3159,66 @@ static X86CPUDefinition builtin_x86_defs[] = { >> { /* end of list */ } >> } >> }, >> + { >> + .name = "Cooperlake", >> + .level = 0xd, >> + .vendor = CPUID_VENDOR_INTEL, >> + .family = 6, >> + .model = 85, >> + .stepping = 10, >> + .features[FEAT_1_EDX] = >> + CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | >> CPUID_MMX | >> + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | >> CPUID_MCA | >> + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | >> CPUID_CX8 | >> + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | >> + CPUID_DE | CPUID_FP87, >> + .features[FEAT_1_ECX] = >> + CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | >> + CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | >> + CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | >> + CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | >> + CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | >> CPUID_EXT_MOVBE | >> + CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, >> + .features[FEAT_8000_0001_EDX] = >> + CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | >> + CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, >> + .features[FEAT_8000_0001_ECX] = >> + CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | >> CPUID_EXT3_3DNOWPREFETCH, >> + .features[FEAT_7_0_EBX] = >> + CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | >> + CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | >> CPUID_7_0_EBX_SMEP | >> + CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | >> CPUID_7_0_EBX_INVPCID | >> + CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | >> CPUID_7_0_EBX_ADX | >> + CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | >> + CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | >> + CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | >> + CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, >> + .features[FEAT_7_0_ECX] = >> + CPUID_7_0_ECX_PKU | >> + CPUID_7_0_ECX_AVX512VNNI, >> + .features[FEAT_7_0_EDX] = >> + CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP | >> + CPUID_7_0_EDX_SPEC_CTRL_SSBD | >> CPUID_7_0_EDX_ARCH_CAPABILITIES, >> + .features[FEAT_ARCH_CAPABILITIES] = >> + MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | >> + MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO, >> + .features[FEAT_7_1_EAX] = >> + CPUID_7_1_EAX_AVX512_BF16, >> + /* >> + * Missing: XSAVES (not supported by some Linux versions, >> + * including v4.1 to v4.12). >> + * KVM doesn't yet expose any XSAVES state save component, >> + * and the only one defined in Skylake (processor tracing) >> + * probably will block migration anyway. >> + */ >> + .features[FEAT_XSAVE] = >> + CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | >> + CPUID_XSAVE_XGETBV1, >> + .features[FEAT_6_EAX] = >> + CPUID_6_EAX_ARAT, >> + .xlevel = 0x80000008, >> + .model_id = "Intel Xeon Processor (Cooperlake)", >> + }, >> { >> .name = "Icelake-Client", >> .level = 0xd, >> > > Hi Eduardo, > > Since this CPU model has been hold for a while, it misses the VMX > features added by Paolo recently. > > Besides, there are two bits PSCHANGE_MC_NO(bit 6) and TAA_NO(bit 8) of > MSR_IA32_ARCH_CAPABILITIES disclosed recently, that are also missed in > this CPU model. > > Should we hold off this and update a new patch with the above features > added? > Or we make this merged and send a new patch to add a new version for the > above? It would be simpler if you can prepare a patch to correct this one. Add the "Fixes: 22a866b6166" tag in it. Thanks! Phil.
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 69f518a21a..de828e29d8 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -3159,6 +3159,66 @@ static X86CPUDefinition builtin_x86_defs[] = { { /* end of list */ } } }, + { + .name = "Cooperlake", + .level = 0xd, + .vendor = CPUID_VENDOR_INTEL, + .family = 6, + .model = 85, + .stepping = 10, + .features[FEAT_1_EDX] = + CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | + CPUID_DE | CPUID_FP87, + .features[FEAT_1_ECX] = + CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | + CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | + CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | + CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | + CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | + CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, + .features[FEAT_8000_0001_EDX] = + CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | + CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, + .features[FEAT_8000_0001_ECX] = + CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, + .features[FEAT_7_0_EBX] = + CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | + CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | + CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | + CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | + CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | + CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | + CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | + CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, + .features[FEAT_7_0_ECX] = + CPUID_7_0_ECX_PKU | + CPUID_7_0_ECX_AVX512VNNI, + .features[FEAT_7_0_EDX] = + CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP | + CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES, + .features[FEAT_ARCH_CAPABILITIES] = + MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | + MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO, + .features[FEAT_7_1_EAX] = + CPUID_7_1_EAX_AVX512_BF16, + /* + * Missing: XSAVES (not supported by some Linux versions, + * including v4.1 to v4.12). + * KVM doesn't yet expose any XSAVES state save component, + * and the only one defined in Skylake (processor tracing) + * probably will block migration anyway. + */ + .features[FEAT_XSAVE] = + CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | + CPUID_XSAVE_XGETBV1, + .features[FEAT_6_EAX] = + CPUID_6_EAX_ARAT, + .xlevel = 0x80000008, + .model_id = "Intel Xeon Processor (Cooperlake)", + }, { .name = "Icelake-Client", .level = 0xd,