Message ID | 20191206213936.v6.57.I673905c51a044952543c14f75f421f5172c34de7@changeid |
---|---|
State | Accepted |
Commit | 28d7d76a86a4e73db27b521d034fb6170df95672 |
Delegated to: | Bin Meng |
Headers | show
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Series |
x86: Add initial support for apollolake
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On Sat, Dec 7, 2019 at 12:49 PM Simon Glass <sjg@chromium.org> wrote: > > For Apollo Lake SPL is run from CAR (cache-as-RAM) which is in a different > location from where SPL must be placed in ROM. In other words, although > SPL runs before SDRAM is set up, it is not execute-in-place (XIP). > > Add a Kconfig option for the ROM position. > > Signed-off-by: Simon Glass <sjg@chromium.org> > Reviewed-by: Bin Meng <bmeng.cn@gmail.com> > --- > > Changes in v6: None > Changes in v5: None > Changes in v4: > - apollolake -> Apollo Lake > > Changes in v3: > - Add SPL condition to the option > > Changes in v2: None > > arch/x86/Kconfig | 5 +++++ > arch/x86/dts/u-boot.dtsi | 4 ++-- > 2 files changed, 7 insertions(+), 2 deletions(-) > applied to u-boot-x86/next, thanks!
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 9d7ff3c07a..1d08cb24fb 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -904,4 +904,9 @@ config X86_OFFSET_U_BOOT depends on HAVE_SYS_TEXT_BASE default SYS_TEXT_BASE +config X86_OFFSET_SPL + hex "Offset of SPL in ROM image" + depends on SPL && X86 + default SPL_TEXT_BASE + endmenu diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi index d84c64880a..fad3e7c951 100644 --- a/arch/x86/dts/u-boot.dtsi +++ b/arch/x86/dts/u-boot.dtsi @@ -45,7 +45,7 @@ }; #endif u-boot-spl { - offset = <CONFIG_SPL_TEXT_BASE>; + offset = <CONFIG_X86_OFFSET_SPL>; }; u-boot-spl-dtb { }; @@ -54,7 +54,7 @@ }; #elif defined(CONFIG_SPL) u-boot-spl-with-ucode-ptr { - offset = <CONFIG_SPL_TEXT_BASE>; + offset = <CONFIG_X86_OFFSET_SPL>; }; u-boot-dtb-with-ucode2 { type = "u-boot-dtb-with-ucode";