@@ -88,6 +88,14 @@ config USB_XHCI_FSL
depends on !SPL_NO_USB
help
Enables support for the on-chip xHCI controller on NXP Layerscape SoCs.
+
+config USB_XHCI_BRCM
+ bool "Broadcom USB3 Host XHCI controller"
+ depends on DM_USB
+ help
+ USB controller based on the Broadcom USB3 IP Core.
+ Supports USB2/3 functionality.
+
endif # USB_XHCI_HCD
config USB_EHCI_HCD
@@ -44,6 +44,7 @@ obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o
obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o
# xhci
+obj-$(CONFIG_USB_XHCI_BRCM) += xhci-brcm.o
obj-$(CONFIG_USB_XHCI_HCD) += xhci.o xhci-mem.o xhci-ring.o
obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o
obj-$(CONFIG_USB_XHCI_DWC3_OF_SIMPLE) += dwc3-of-simple.o
new file mode 100644
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Broadcom.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <usb.h>
+#include <asm/io.h>
+#include "xhci.h"
+
+#define DRD2U3H_XHC_REGS_AXIWRA 0xC08
+#define DRD2U3H_XHC_REGS_AXIRDA 0xC0C
+
+#define USBAXI_AWCACHE 0xF
+#define USBAXI_ARCACHE 0xF
+#define USBAXI_AWPROT 0x8
+#define USBAXI_ARPROT 0x8
+#define USBAXIWR_SA_VAL ((USBAXI_AWCACHE << 4) | USBAXI_AWPROT)
+#define USBAXIWR_SA_MASK 0xFF
+#define USBAXIWR_UA_VAL (((USBAXI_AWCACHE << 4) | USBAXI_AWPROT) << 16)
+#define USBAXIWR_UA_MASK (0xFF << 16)
+#define USBAXIRD_SA_VAL ((USBAXI_ARCACHE << 4) | USBAXI_ARPROT)
+#define USBAXIRD_SA_MASK 0xFF
+#define USBAXIRD_UA_VAL (((USBAXI_ARCACHE << 4) | USBAXI_ARPROT) << 16)
+#define USBAXIRD_UA_MASK (0xFF << 16)
+
+struct brcm_xhci_platdata {
+ unsigned int arcache;
+ unsigned int awcache;
+};
+
+static int xhci_brcm_probe(struct udevice *dev)
+{
+ struct xhci_hccr *hcd;
+ struct xhci_hcor *hcor;
+ struct brcm_xhci_platdata *plat = dev_get_platdata(dev);
+ uintptr_t hc_base;
+ int len, ret = 0;
+
+ if (!plat) {
+ dev_err(dev, "Can't get xHCI Plat data\n");
+ return -ENOMEM;
+ }
+
+ hcd = dev_read_addr_ptr(dev);
+ if (!hcd) {
+ dev_err(dev, "Can't get the xHCI register base address\n");
+ return -ENXIO;
+ }
+
+ hc_base = (uintptr_t)hcd;
+ len = HC_LENGTH(xhci_readl(&hcd->cr_capbase));
+ hcor = (struct xhci_hcor *)(hc_base + len);
+
+ /* Save the default values of AXI read and write attributes */
+ plat->awcache = readl(hc_base + DRD2U3H_XHC_REGS_AXIWRA);
+ plat->arcache = readl(hc_base + DRD2U3H_XHC_REGS_AXIRDA);
+
+ /* Enable AXI read and write attributes. */
+ clrsetbits_le32((hc_base + DRD2U3H_XHC_REGS_AXIWRA),
+ (USBAXIWR_UA_MASK | USBAXIWR_SA_MASK),
+ (USBAXIWR_UA_VAL | USBAXIWR_SA_VAL));
+ clrsetbits_le32((hc_base + DRD2U3H_XHC_REGS_AXIRDA),
+ (USBAXIRD_UA_MASK | USBAXIRD_SA_MASK),
+ (USBAXIRD_UA_VAL | USBAXIRD_SA_VAL));
+
+ ret = xhci_register(dev, hcd, hcor);
+ if (ret)
+ dev_err(dev, "Failed to register xHCI\n");
+
+ return ret;
+}
+
+static int xhci_brcm_deregister(struct udevice *dev)
+{
+ struct brcm_xhci_platdata *plat = dev_get_platdata(dev);
+ uintptr_t hc_base;
+
+ hc_base = (uintptr_t)dev_read_addr(dev);
+
+ /* Restore the default values for AXI read and write attributes */
+ writel(plat->awcache, hc_base + DRD2U3H_XHC_REGS_AXIWRA);
+ writel(plat->arcache, hc_base + DRD2U3H_XHC_REGS_AXIRDA);
+
+ return xhci_deregister(dev);
+}
+
+static const struct udevice_id xhci_brcm_ids[] = {
+ { .compatible = "brcm,generic-xhci" },
+ { }
+};
+
+U_BOOT_DRIVER(usb_xhci) = {
+ .name = "xhci_brcm",
+ .id = UCLASS_USB,
+ .probe = xhci_brcm_probe,
+ .remove = xhci_brcm_deregister,
+ .ops = &xhci_usb_ops,
+ .of_match = xhci_brcm_ids,
+ .platdata_auto_alloc_size = sizeof(struct brcm_xhci_platdata),
+ .priv_auto_alloc_size = sizeof(struct xhci_ctrl),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};