| Message ID | 20191120164912.32384-3-ehabkost@redhat.com |
|---|---|
| State | New |
| Headers | show |
| Series | i386: Add new versions of Skylake/Cascadelake/Icelake without TSX | expand |
On Wed, Nov 20, 2019 at 01:49:12PM -0300, Eduardo Habkost wrote: > We have been trying to avoid adding new aliases for CPU model > versions, but in the case of changes in defaults introduced by > the TAA mitigation patches, the aliases might help avoid user > confusion when applying host software updates. > > Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Tested-by: Kashyap Chamarthy <kchamart@redhat.com> https://lists.gnu.org/archive/html/qemu-devel/2019-11/msg03501.html - - - Should we (can do it, if you already don't have a patch WIP for it) also update this file to reflect this? https://git.qemu.org/?p=qemu.git;a=blob;f=docs/qemu-cpu-models.texi While at it ... I wonder if it's worth making a separte doc (versioned-cpu-models.rst) explaining the versioned CPU models, usage, etc. There was a very useful discussion between you and Dan Berrangé on this list (Message-Id: <20190625050008.12789-5-ehabkost@redhat.com>, the first version of the thread: "[PATCH 4/6] i386: Infrastructure for versioned CPU models"). Could potentially incorporate some of that content. > --- > target/i386/cpu.c | 5 +++++ > 1 file changed, 5 insertions(+) [...]
On Thu, Nov 21, 2019 at 03:12:45PM +0100, Kashyap Chamarthy wrote: > On Wed, Nov 20, 2019 at 01:49:12PM -0300, Eduardo Habkost wrote: > > We have been trying to avoid adding new aliases for CPU model > > versions, but in the case of changes in defaults introduced by > > the TAA mitigation patches, the aliases might help avoid user > > confusion when applying host software updates. > > > > Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> > > Tested-by: Kashyap Chamarthy <kchamart@redhat.com> > > https://lists.gnu.org/archive/html/qemu-devel/2019-11/msg03501.html Thanks! > > - - - > > Should we (can do it, if you already don't have a patch WIP for it) > also update this file to reflect this? > https://git.qemu.org/?p=qemu.git;a=blob;f=docs/qemu-cpu-models.texi Yes, we should. Thanks for the reminder! > > While at it ... I wonder if it's worth making a separte doc > (versioned-cpu-models.rst) explaining the versioned CPU models, usage, > etc. > > There was a very useful discussion between you and Dan Berrangé on this > list (Message-Id: <20190625050008.12789-5-ehabkost@redhat.com>, the > first version of the thread: "[PATCH 4/6] i386: Infrastructure for > versioned CPU models"). Could potentially incorporate some of that > content. > We should, but I don't think I can do it in time for QEMU 4.2. > > --- > > target/i386/cpu.c | 5 +++++ > > 1 file changed, 5 insertions(+) > > [...] > > -- > /kashyap
On Mon, Nov 25, 2019 at 11:21:10AM -0300, Eduardo Habkost wrote: > On Thu, Nov 21, 2019 at 03:12:45PM +0100, Kashyap Chamarthy wrote: > > On Wed, Nov 20, 2019 at 01:49:12PM -0300, Eduardo Habkost wrote: [...] > > - - - > > > > Should we (can do it, if you already don't have a patch WIP for it) > > also update this file to reflect this? > > https://git.qemu.org/?p=qemu.git;a=blob;f=docs/qemu-cpu-models.texi > > Yes, we should. Thanks for the reminder! > > > > > While at it ... I wonder if it's worth making a separte doc > > (versioned-cpu-models.rst) explaining the versioned CPU models, usage, > > etc. > > > > There was a very useful discussion between you and Dan Berrangé on this > > list (Message-Id: <20190625050008.12789-5-ehabkost@redhat.com>, the > > first version of the thread: "[PATCH 4/6] i386: Infrastructure for > > versioned CPU models"). Could potentially incorporate some of that > > content. > > > > We should, but I don't think I can do it in time for QEMU 4.2. It's okay; that can wait for post-4.2. [...]
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 0267e08612..56eb98ef35 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2476,6 +2476,7 @@ static X86CPUDefinition builtin_x86_defs[] = { }, { .version = 3, + .alias = "Skylake-Client-noTSX-IBRS", .props = (PropValue[]) { { "hle", "off" }, { "rtm", "off" }, @@ -2551,6 +2552,7 @@ static X86CPUDefinition builtin_x86_defs[] = { }, { .version = 3, + .alias = "Skylake-Server-noTSX-IBRS", .props = (PropValue[]) { { "hle", "off" }, { "rtm", "off" }, @@ -2625,6 +2627,7 @@ static X86CPUDefinition builtin_x86_defs[] = { }, }, { .version = 3, + .alias = "Cascadelake-Server-noTSX", .props = (PropValue[]) { { "hle", "off" }, { "rtm", "off" }, @@ -2692,6 +2695,7 @@ static X86CPUDefinition builtin_x86_defs[] = { { .version = 1 }, { .version = 2, + .alias = "Icelake-Client-noTSX", .props = (PropValue[]) { { "hle", "off" }, { "rtm", "off" }, @@ -2762,6 +2766,7 @@ static X86CPUDefinition builtin_x86_defs[] = { { .version = 1 }, { .version = 2, + .alias = "Icelake-Server-noTSX", .props = (PropValue[]) { { "hle", "off" }, { "rtm", "off" },
We have been trying to avoid adding new aliases for CPU model versions, but in the case of changes in defaults introduced by the TAA mitigation patches, the aliases might help avoid user confusion when applying host software updates. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> --- target/i386/cpu.c | 5 +++++ 1 file changed, 5 insertions(+)