| Message ID | 1573560684-48104-3-git-send-email-yash.shah@sifive.com |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | GPIO & Hierarchy IRQ support for HiFive Unleashed | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success |
On Tue, Nov 12, 2019 at 12:12:06PM +0000, Yash Shah wrote: > DT documentation for GPIO controller added. > > Signed-off-by: Wesley W. Terpstra <wesley@sifive.com> > [Atish: Compatible string update] > Signed-off-by: Atish Patra <atish.patra@wdc.com> > Signed-off-by: Yash Shah <yash.shah@sifive.com> > --- > .../devicetree/bindings/gpio/gpio-sifive.txt | 33 ++++++++++++++++++++++ > 1 file changed, 33 insertions(+) > create mode 100644 Documentation/devicetree/bindings/gpio/gpio-sifive.txt Please make this a schema. See Documentation/devicetree/writing-schema.rst. > > diff --git a/Documentation/devicetree/bindings/gpio/gpio-sifive.txt b/Documentation/devicetree/bindings/gpio/gpio-sifive.txt > new file mode 100644 > index 0000000..d3416d5 > --- /dev/null > +++ b/Documentation/devicetree/bindings/gpio/gpio-sifive.txt > @@ -0,0 +1,33 @@ > +SiFive GPIO controller bindings > + > +Required properties: > +- compatible: Should be "sifive,<chip>-gpio" and "sifive,gpio<version>". > + Supported compatible strings are: "sifive,fu540-c000-gpio" for the SiFive > + GPIO v0 as integrated onto the SiFive FU540 chip, and "sifive,gpio0" for the > + SiFive GPIO v0 IP block with no chip integration tweaks. > + Please refer to sifive-blocks-ip-versioning.txt for details. > +- reg: Physical base address and length of the controller's registers. > +- clocks: Should contain a clock identifier for the GPIO's parent clock. > +- #gpio-cells : Should be 2 > + - The first cell is the GPIO offset number. > + - The second cell indicates the polarity of the GPIO > +- gpio-controller : Marks the device node as a GPIO controller. > +- interrupt-controller: Marks the device node as an interrupt controller. > +- #interrupt-cells : Should be 2. > + - The first cell is the GPIO offset number within the GPIO controller. > + - The second cell is the edge/level to use for interrupt generation. > +- interrupts: Specify the interrupts, one per GPIO How many GPIOs? > + > +Example: > + > +gpio: gpio@10060000 { > + compatible = "sifive,fu540-c000-gpio","sifive,gpio0"; space ^ > + interrupt-parent = <&plic>; > + interrupts = <7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22>; > + reg = <0x0 0x10060000 0x0 0x1000>; > + clocks = <&tlclk>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > +}; > -- > 2.7.4 >
diff --git a/Documentation/devicetree/bindings/gpio/gpio-sifive.txt b/Documentation/devicetree/bindings/gpio/gpio-sifive.txt new file mode 100644 index 0000000..d3416d5 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-sifive.txt @@ -0,0 +1,33 @@ +SiFive GPIO controller bindings + +Required properties: +- compatible: Should be "sifive,<chip>-gpio" and "sifive,gpio<version>". + Supported compatible strings are: "sifive,fu540-c000-gpio" for the SiFive + GPIO v0 as integrated onto the SiFive FU540 chip, and "sifive,gpio0" for the + SiFive GPIO v0 IP block with no chip integration tweaks. + Please refer to sifive-blocks-ip-versioning.txt for details. +- reg: Physical base address and length of the controller's registers. +- clocks: Should contain a clock identifier for the GPIO's parent clock. +- #gpio-cells : Should be 2 + - The first cell is the GPIO offset number. + - The second cell indicates the polarity of the GPIO +- gpio-controller : Marks the device node as a GPIO controller. +- interrupt-controller: Marks the device node as an interrupt controller. +- #interrupt-cells : Should be 2. + - The first cell is the GPIO offset number within the GPIO controller. + - The second cell is the edge/level to use for interrupt generation. +- interrupts: Specify the interrupts, one per GPIO + +Example: + +gpio: gpio@10060000 { + compatible = "sifive,fu540-c000-gpio","sifive,gpio0"; + interrupt-parent = <&plic>; + interrupts = <7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22>; + reg = <0x0 0x10060000 0x0 0x1000>; + clocks = <&tlclk>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; +};