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[v6,1/2] dt/bindings: clk: Add YAML schemas for LS1028A Display Clock bindings

Message ID 20191105090221.45381-1-wen.he_1@nxp.com
State Not Applicable, archived
Headers show
Series [v6,1/2] dt/bindings: clk: Add YAML schemas for LS1028A Display Clock bindings | expand

Commit Message

Wen He Nov. 5, 2019, 9:02 a.m. UTC 
LS1028A has a clock domain PXLCLK0 used for provide pixel clocks to Display
output interface. Add a YAML schema for this.

Signed-off-by: Wen He <wen.he_1@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
change in v6:
	- no change	

 .../devicetree/bindings/clock/fsl,plldig.yaml | 43 +++++++++++++++++++
 1 file changed, 43 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/fsl,plldig.yaml

Comments

Leo Li Nov. 5, 2019, 9:10 p.m. UTC | #1 
> -----Original Message-----
> From: Wen He <wen.he_1@nxp.com>
> Sent: Tuesday, November 5, 2019 3:02 AM
> To: linux-devel@linux.nxdi.nxp.com; Michael Turquette
> <mturquette@baylibre.com>; Stephen Boyd <sboyd@kernel.org>; Rob
> Herring <robh+dt@kernel.org>; Mark Rutland <mark.rutland@arm.com>;
> Leo Li <leoyang.li@nxp.com>; devicetree@vger.kernel.org; linux-
> clk@vger.kernel.org; linux-kernel@vger.kernel.org
> Cc: Wen He <wen.he_1@nxp.com>
> Subject: [v6 2/2] clk: ls1028a: Add clock driver for Display output interface
> 
> Add clock driver for QorIQ LS1028A Display output interfaces(LCD, DPHY), as
> implemented in TSMC CLN28HPM PLL, this PLL supports the programmable
> integer division and range of the display output pixel clock's 27-594MHz.
> 
> Signed-off-by: Wen He <wen.he_1@nxp.com>
> ---
> change in v6:
>         - Add get the best loop multiplication divider from DTS.
> 
>  drivers/clk/Kconfig      |  10 ++
>  drivers/clk/Makefile     |   1 +
>  drivers/clk/clk-plldig.c | 294
> +++++++++++++++++++++++++++++++++++++++
>  3 files changed, 305 insertions(+)
>  create mode 100644 drivers/clk/clk-plldig.c
> 
> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index
> 0530bebfc25a..9f6b0196c604 100644
> --- a/drivers/clk/Kconfig
> +++ b/drivers/clk/Kconfig
> @@ -218,6 +218,16 @@ config CLK_QORIQ
>  	  This adds the clock driver support for Freescale QorIQ platforms
>  	  using common clock framework.
> 
> +config CLK_LS1028A_PLLDIG
> +        tristate "Clock driver for LS1028A Display output"
> +        depends on ARCH_LAYERSCAPE || COMPILE_TEST
> +        default ARCH_LAYERSCAPE
> +        help
> +          This driver support the Display output interfaces(LCD, DPHY) pixel
> clocks
> +          of the QorIQ Layerscape LS1028A, as implemented TSMC CLN28HPM
> PLL. Not all
> +          features of the PLL are currently supported by the driver. By default,
> +          configured bypass mode with this PLL.
> +
>  config COMMON_CLK_XGENE
>  	bool "Clock driver for APM XGene SoC"
>  	default ARCH_XGENE
> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index
> 0138fb14e6f8..d23b7464aba8 100644
> --- a/drivers/clk/Makefile
> +++ b/drivers/clk/Makefile
> @@ -45,6 +45,7 @@ obj-$(CONFIG_COMMON_CLK_OXNAS)		+=
> clk-oxnas.o
>  obj-$(CONFIG_COMMON_CLK_PALMAS)		+= clk-palmas.o
>  obj-$(CONFIG_COMMON_CLK_PWM)		+= clk-pwm.o
>  obj-$(CONFIG_CLK_QORIQ)			+= clk-qoriq.o
> +obj-$(CONFIG_CLK_LS1028A_PLLDIG)	+= clk-plldig.o

Wrong ordering.  This section of Makefile requires ordering by driver file name:

# hardware specific clock types
# please keep this section sorted lexicographically by file path name

>  obj-$(CONFIG_COMMON_CLK_RK808)		+= clk-rk808.o
>  obj-$(CONFIG_COMMON_CLK_HI655X)		+= clk-hi655x.o
>  obj-$(CONFIG_COMMON_CLK_S2MPS11)	+= clk-s2mps11.o
> diff --git a/drivers/clk/clk-plldig.c b/drivers/clk/clk-plldig.c new file mode
> 100644 index 000000000000..57d8121990bd
> --- /dev/null
> +++ b/drivers/clk/clk-plldig.c
> @@ -0,0 +1,294 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright 2019 NXP
> + *
> + * Clock driver for LS1028A Display output interfaces(LCD, DPHY).
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/device.h>
> +#include <linux/module.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +#include <linux/bitfield.h>
> +
> +/* PLLDIG register offsets and bit masks */
> +#define PLLDIG_REG_PLLSR            0x24
> +#define PLLDIG_REG_PLLDV            0x28
> +#define PLLDIG_REG_PLLFM            0x2c
> +#define PLLDIG_REG_PLLFD            0x30
> +#define PLLDIG_REG_PLLCAL1          0x38
> +#define PLLDIG_REG_PLLCAL2          0x3c
> +#define PLLDIG_LOCK_MASK            BIT(2)
> +#define PLLDIG_REG_FIELD_SSCGBYP    BIT(30)
> +#define PLLDIG_REG_FIELD_FDEN       BIT(30)
> +#define PLLDIG_REG_FIELD_DTHDIS     GENMASK(17, 16)
> +#define PLLDIG_REG_FIELD_MULT       GENMASK(7, 0)
> +#define PLLDIG_REG_FIELD_RFDPHI1    GENMASK(30, 25)
> +
> +/* Minimum output clock frequency, in Hz */ #define PHI1_MIN_FREQ
> +27000000
> +
> +/* Maximum output clock frequency, in Hz */ #define PHI1_MAX_FREQ
> +600000000
> +
> +/* Maximum of the divider */
> +#define MAX_RFDPHI1          63
> +
> +/*
> + * Clock configuration relationship between the PHI1
> +frequency(fpll_phi) and
> + * the output frequency of the PLL is determined by the PLLDV,
> +according to
> + * the following equation:
> + * fpll_phi = (pll_ref * mfd) / div_rfdphi1  */ struct
> +plldig_phi1_param {
> +	unsigned long rate;
> +	unsigned int rfdphi1;
> +	unsigned int mfd;
> +};
> +
> +static const struct clk_parent_data parent_data[] = {
> +	{.index = 0},
> +};
> +
> +struct clk_plldig {
> +	struct clk_hw hw;
> +	void __iomem *regs;
> +	unsigned int mfd;
> +};
> +
> +#define to_clk_plldig(_hw)	container_of(_hw, struct clk_plldig, hw)
> +
> +static int plldig_enable(struct clk_hw *hw) {
> +	struct clk_plldig *data = to_clk_plldig(hw);
> +	u32 val;
> +
> +	val = readl(data->regs + PLLDIG_REG_PLLFM);
> +	/*
> +	 * Use Bypass mode with PLL off by default, the frequency overshoot
> +	 * detector output was disable. SSCG Bypass mode should be enable.
> +	 */
> +	val |= PLLDIG_REG_FIELD_SSCGBYP;
> +	writel(val, data->regs + PLLDIG_REG_PLLFM);
> +
> +	val = readl(data->regs + PLLDIG_REG_PLLFD);
> +	/* Disable dither and Sigma delta modulation in bypass mode */
> +	val |= FIELD_PREP(PLLDIG_REG_FIELD_FDEN, 0x1) |
> +	       FIELD_PREP(PLLDIG_REG_FIELD_DTHDIS, 0x3);
> +
> +	writel(val, data->regs + PLLDIG_REG_PLLFD);
> +
> +	return 0;
> +}
> +
> +static void plldig_disable(struct clk_hw *hw) {
> +	struct clk_plldig *data = to_clk_plldig(hw);
> +	u32 val;
> +
> +	val = readl(data->regs + PLLDIG_REG_PLLFM);
> +
> +	val &= ~PLLDIG_REG_FIELD_SSCGBYP;
> +	val |= FIELD_PREP(PLLDIG_REG_FIELD_SSCGBYP, 0x0);
> +
> +	writel(val, data->regs + PLLDIG_REG_PLLFM); }
> +
> +static int plldig_is_enabled(struct clk_hw *hw) {
> +	struct clk_plldig *data = to_clk_plldig(hw);
> +
> +	return (readl(data->regs + PLLDIG_REG_PLLFM) &
> +			      PLLDIG_REG_FIELD_SSCGBYP);
> +}
> +
> +static unsigned long plldig_recalc_rate(struct clk_hw *hw,
> +		unsigned long parent_rate)
> +{
> +	struct clk_plldig *data = to_clk_plldig(hw);
> +	u32 mult, div, val;
> +
> +	val = readl(data->regs + PLLDIG_REG_PLLDV);
> +
> +	/* Check if PLL is bypassed */
> +	if (val & PLLDIG_REG_FIELD_SSCGBYP)
> +		return parent_rate;
> +
> +	/* Checkout multiplication factor divider value */
> +	mult = FIELD_GET(PLLDIG_REG_FIELD_MULT, val);
> +
> +	/* Checkout divider value of the output frequency */
> +	div = FIELD_GET(PLLDIG_REG_FIELD_RFDPHI1, val);
> +
> +	return (parent_rate * mult) / div;
> +}
> +
> +static int plldig_calc_target_rate(unsigned long target_rate,
> +				   unsigned long parent_rate,
> +				   struct plldig_phi1_param *phi1)
> +{
> +	unsigned int div, ret;
> +	unsigned long round_rate;
> +
> +	/* Range limitation of the request target rate */
> +	if (target_rate > PHI1_MAX_FREQ)
> +		target_rate = PHI1_MAX_FREQ;
> +	else if (target_rate < PHI1_MIN_FREQ)
> +		target_rate = PHI1_MIN_FREQ;
> +
> +	/*
> +	 * Firstly, check the request target rate whether is divisible
> +	 * by the best VCO frequency.
> +	 */
> +	round_rate = parent_rate * phi1->mfd;
> +	div = round_rate / target_rate;
> +	if (!div || div > MAX_RFDPHI1)
> +		return -EINVAL;
> +
> +	ret = round_rate % target_rate;
> +	if (ret) {
> +		/*
> +		 * Rounded down the request target rate, VESA specifies
> +		 * 0.5% pixel clock tolerance, therefore this algorithm
> +		 * can able to compatible a lot of request rates within
> +		 * range of the tolerance.
> +		 */
> +		round_rate += (target_rate / 2);
> +		div = round_rate / target_rate;
> +		if (!div || div > MAX_RFDPHI1)
> +			return -EINVAL;
> +	}
> +
> +	phi1->rfdphi1 = div;
> +	phi1->rate = target_rate;
> +
> +	return 0;
> +}
> +
> +static int plldig_determine_rate(struct clk_hw *hw,
> +				 struct clk_rate_request *req)
> +{
> +	int ret;
> +	unsigned long parent_rate;
> +	struct clk_hw *parent;
> +	struct plldig_phi1_param phi1_param;
> +	struct clk_plldig *data = to_clk_plldig(hw);
> +
> +	if (!req->rate)
> +		return -ERANGE;
> +
> +	phi1_param.mfd = data->mfd;
> +	parent = clk_hw_get_parent(hw);
> +	parent_rate = clk_hw_get_rate(parent);
> +
> +	ret = plldig_calc_target_rate(req->rate, parent_rate, &phi1_param);
> +	if (ret)
> +		return ret;
> +
> +	req->rate = phi1_param.rate;
> +
> +	return 0;
> +}
> +
> +static int plldig_set_rate(struct clk_hw *hw, unsigned long rate,
> +		unsigned long parent_rate)
> +{
> +	struct clk_plldig *data = to_clk_plldig(hw);
> +	struct plldig_phi1_param phi1_param;
> +	unsigned int val, cond;
> +	int ret;
> +
> +	ret = plldig_calc_target_rate(rate, parent_rate, &phi1_param);
> +	if (ret)
> +		return ret;
> +
> +	val = readl(data->regs + PLLDIG_REG_PLLDV);
> +	val = FIELD_PREP(PLLDIG_REG_FIELD_MULT, data->mfd) |
> +	      FIELD_PREP(PLLDIG_REG_FIELD_RFDPHI1, phi1_param.rfdphi1);
> +
> +	writel(val, data->regs + PLLDIG_REG_PLLDV);
> +
> +	/* delay 200us make sure that old lock state is cleared */
> +	udelay(200);
> +
> +	/* Wait until PLL is locked or timeout (maximum 1000 usecs) */
> +	return readl_poll_timeout_atomic(data->regs + PLLDIG_REG_PLLSR,
> cond,
> +					 cond & PLLDIG_LOCK_MASK, 0,
> +					 USEC_PER_MSEC);
> +}
> +
> +static const struct clk_ops plldig_clk_ops = {
> +	.enable = plldig_enable,
> +	.disable = plldig_disable,
> +	.is_enabled = plldig_is_enabled,
> +	.recalc_rate = plldig_recalc_rate,
> +	.determine_rate = plldig_determine_rate,
> +	.set_rate = plldig_set_rate,
> +};
> +
> +static int plldig_clk_probe(struct platform_device *pdev) {
> +	struct clk_plldig *data;
> +	struct resource *mem;
> +	struct device *dev = &pdev->dev;
> +	int ret;
> +
> +	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
> +	if (!data)
> +		return -ENOMEM;
> +
> +	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	data->regs = devm_ioremap_resource(dev, mem);
> +	if (IS_ERR(data->regs))
> +		return PTR_ERR(data->regs);
> +
> +	 /*
> +	  * Support to get the best loop multiplication divider value
> +	  * from DTS file, since this PLL can't changed this value on
> +	  * the fly, write the fixed value.
> +	  */
> +	ret = of_property_read_u32(dev->of_node, "best-mfd", &data-
> >mfd);
> +	if (ret)
> +		data->mfd = 0x2c;
> +
> +	data->hw.init = CLK_HW_INIT_PARENTS_DATA("dpclk",
> +						 parent_data,
> +						 &plldig_clk_ops,
> +						 0);
> +
> +	ret = devm_clk_hw_register(dev, &data->hw);
> +	if (ret) {
> +		dev_err(dev, "failed to register %s clock\n",
> +						dev->of_node->name);
> +		return ret;
> +	}
> +
> +	return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
> +					   &data->hw);
> +}
> +
> +static const struct of_device_id plldig_clk_id[] = {
> +	{ .compatible = "fsl,ls1028a-plldig"},
> +	{ }
> +};
> +MODULE_DEVICE_TABLE(of, plldig_clk_id);
> +
> +static struct platform_driver plldig_clk_driver = {
> +	.driver = {
> +		.name = "plldig-clock",
> +		.of_match_table = plldig_clk_id,
> +	},
> +	.probe = plldig_clk_probe,
> +};
> +module_platform_driver(plldig_clk_driver);
> +
> +MODULE_LICENSE("GPL v2");
> +MODULE_AUTHOR("Wen He <wen.he_1@nxp.com>");
> MODULE_DESCRIPTION("LS1028A
> +Display output interface pixel clock driver");
> --
> 2.17.1
Wen He Nov. 7, 2019, 3:13 a.m. UTC | #2 
> -----Original Message-----
> From: Leo Li <leoyang.li@nxp.com>
> Sent: 2019年11月6日 5:11
> To: Wen He <wen.he_1@nxp.com>; linux-devel@linux.nxdi.nxp.com; Michael
> Turquette <mturquette@baylibre.com>; Stephen Boyd <sboyd@kernel.org>;
> Rob Herring <robh+dt@kernel.org>; Mark Rutland <mark.rutland@arm.com>;
> devicetree@vger.kernel.org; linux-clk@vger.kernel.org;
> linux-kernel@vger.kernel.org
> Cc: Wen He <wen.he_1@nxp.com>
> Subject: RE: [v6 2/2] clk: ls1028a: Add clock driver for Display output interface
> 
> 
> 
> > -----Original Message-----
> > From: Wen He <wen.he_1@nxp.com>
> > Sent: Tuesday, November 5, 2019 3:02 AM
> > To: linux-devel@linux.nxdi.nxp.com; Michael Turquette
> > <mturquette@baylibre.com>; Stephen Boyd <sboyd@kernel.org>; Rob
> > Herring <robh+dt@kernel.org>; Mark Rutland <mark.rutland@arm.com>;
> Leo
> > Li <leoyang.li@nxp.com>; devicetree@vger.kernel.org; linux-
> > clk@vger.kernel.org; linux-kernel@vger.kernel.org
> > Cc: Wen He <wen.he_1@nxp.com>
> > Subject: [v6 2/2] clk: ls1028a: Add clock driver for Display output
> > interface
> >
> > Add clock driver for QorIQ LS1028A Display output interfaces(LCD,
> > DPHY), as implemented in TSMC CLN28HPM PLL, this PLL supports the
> > programmable integer division and range of the display output pixel clock's
> 27-594MHz.
> >
> > Signed-off-by: Wen He <wen.he_1@nxp.com>
> > ---
> > change in v6:
> >         - Add get the best loop multiplication divider from DTS.
> >
> >  drivers/clk/Kconfig      |  10 ++
> >  drivers/clk/Makefile     |   1 +
> >  drivers/clk/clk-plldig.c | 294
> > +++++++++++++++++++++++++++++++++++++++
> >  3 files changed, 305 insertions(+)
> >  create mode 100644 drivers/clk/clk-plldig.c
> >
> > diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index
> > 0530bebfc25a..9f6b0196c604 100644
> > --- a/drivers/clk/Kconfig
> > +++ b/drivers/clk/Kconfig
> > @@ -218,6 +218,16 @@ config CLK_QORIQ
> >  	  This adds the clock driver support for Freescale QorIQ platforms
> >  	  using common clock framework.
> >
> > +config CLK_LS1028A_PLLDIG
> > +        tristate "Clock driver for LS1028A Display output"
> > +        depends on ARCH_LAYERSCAPE || COMPILE_TEST
> > +        default ARCH_LAYERSCAPE
> > +        help
> > +          This driver support the Display output interfaces(LCD,
> > +DPHY) pixel
> > clocks
> > +          of the QorIQ Layerscape LS1028A, as implemented TSMC
> > + CLN28HPM
> > PLL. Not all
> > +          features of the PLL are currently supported by the driver. By
> default,
> > +          configured bypass mode with this PLL.
> > +
> >  config COMMON_CLK_XGENE
> >  	bool "Clock driver for APM XGene SoC"
> >  	default ARCH_XGENE
> > diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index
> > 0138fb14e6f8..d23b7464aba8 100644
> > --- a/drivers/clk/Makefile
> > +++ b/drivers/clk/Makefile
> > @@ -45,6 +45,7 @@ obj-$(CONFIG_COMMON_CLK_OXNAS)		+=
> > clk-oxnas.o
> >  obj-$(CONFIG_COMMON_CLK_PALMAS)		+= clk-palmas.o
> >  obj-$(CONFIG_COMMON_CLK_PWM)		+= clk-pwm.o
> >  obj-$(CONFIG_CLK_QORIQ)			+= clk-qoriq.o
> > +obj-$(CONFIG_CLK_LS1028A_PLLDIG)	+= clk-plldig.o
> 
> Wrong ordering.  This section of Makefile requires ordering by driver file
> name:
> 
> # hardware specific clock types
> # please keep this section sorted lexicographically by file path name
> 

Hi Leo,

Stephen once suggest the Kconfig variable name should be given a more
specific name like CLK_LS1028A_PLLDIG, so I have to changed it.

Hi Stephen,

How do you think?

Best Regards,
Wen

> >  obj-$(CONFIG_COMMON_CLK_RK808)		+= clk-rk808.o
> >  obj-$(CONFIG_COMMON_CLK_HI655X)		+= clk-hi655x.o
> >  obj-$(CONFIG_COMMON_CLK_S2MPS11)	+= clk-s2mps11.o
> > diff --git a/drivers/clk/clk-plldig.c b/drivers/clk/clk-plldig.c new
> > file mode
> > 100644 index 000000000000..57d8121990bd
> > --- /dev/null
> > +++ b/drivers/clk/clk-plldig.c
> > @@ -0,0 +1,294 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright 2019 NXP
> > + *
> > + * Clock driver for LS1028A Display output interfaces(LCD, DPHY).
> > + */
> > +
> > +#include <linux/clk-provider.h>
> > +#include <linux/device.h>
> > +#include <linux/module.h>
> > +#include <linux/err.h>
> > +#include <linux/io.h>
> > +#include <linux/iopoll.h>
> > +#include <linux/of.h>
> > +#include <linux/of_address.h>
> > +#include <linux/of_device.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/slab.h>
> > +#include <linux/bitfield.h>
> > +
> > +/* PLLDIG register offsets and bit masks */
> > +#define PLLDIG_REG_PLLSR            0x24
> > +#define PLLDIG_REG_PLLDV            0x28
> > +#define PLLDIG_REG_PLLFM            0x2c
> > +#define PLLDIG_REG_PLLFD            0x30
> > +#define PLLDIG_REG_PLLCAL1          0x38
> > +#define PLLDIG_REG_PLLCAL2          0x3c
> > +#define PLLDIG_LOCK_MASK            BIT(2)
> > +#define PLLDIG_REG_FIELD_SSCGBYP    BIT(30)
> > +#define PLLDIG_REG_FIELD_FDEN       BIT(30)
> > +#define PLLDIG_REG_FIELD_DTHDIS     GENMASK(17, 16)
> > +#define PLLDIG_REG_FIELD_MULT       GENMASK(7, 0)
> > +#define PLLDIG_REG_FIELD_RFDPHI1    GENMASK(30, 25)
> > +
> > +/* Minimum output clock frequency, in Hz */ #define PHI1_MIN_FREQ
> > +27000000
> > +
> > +/* Maximum output clock frequency, in Hz */ #define PHI1_MAX_FREQ
> > +600000000
> > +
> > +/* Maximum of the divider */
> > +#define MAX_RFDPHI1          63
> > +
> > +/*
> > + * Clock configuration relationship between the PHI1
> > +frequency(fpll_phi) and
> > + * the output frequency of the PLL is determined by the PLLDV,
> > +according to
> > + * the following equation:
> > + * fpll_phi = (pll_ref * mfd) / div_rfdphi1  */ struct
> > +plldig_phi1_param {
> > +	unsigned long rate;
> > +	unsigned int rfdphi1;
> > +	unsigned int mfd;
> > +};
> > +
> > +static const struct clk_parent_data parent_data[] = {
> > +	{.index = 0},
> > +};
> > +
> > +struct clk_plldig {
> > +	struct clk_hw hw;
> > +	void __iomem *regs;
> > +	unsigned int mfd;
> > +};
> > +
> > +#define to_clk_plldig(_hw)	container_of(_hw, struct clk_plldig, hw)
> > +
> > +static int plldig_enable(struct clk_hw *hw) {
> > +	struct clk_plldig *data = to_clk_plldig(hw);
> > +	u32 val;
> > +
> > +	val = readl(data->regs + PLLDIG_REG_PLLFM);
> > +	/*
> > +	 * Use Bypass mode with PLL off by default, the frequency overshoot
> > +	 * detector output was disable. SSCG Bypass mode should be enable.
> > +	 */
> > +	val |= PLLDIG_REG_FIELD_SSCGBYP;
> > +	writel(val, data->regs + PLLDIG_REG_PLLFM);
> > +
> > +	val = readl(data->regs + PLLDIG_REG_PLLFD);
> > +	/* Disable dither and Sigma delta modulation in bypass mode */
> > +	val |= FIELD_PREP(PLLDIG_REG_FIELD_FDEN, 0x1) |
> > +	       FIELD_PREP(PLLDIG_REG_FIELD_DTHDIS, 0x3);
> > +
> > +	writel(val, data->regs + PLLDIG_REG_PLLFD);
> > +
> > +	return 0;
> > +}
> > +
> > +static void plldig_disable(struct clk_hw *hw) {
> > +	struct clk_plldig *data = to_clk_plldig(hw);
> > +	u32 val;
> > +
> > +	val = readl(data->regs + PLLDIG_REG_PLLFM);
> > +
> > +	val &= ~PLLDIG_REG_FIELD_SSCGBYP;
> > +	val |= FIELD_PREP(PLLDIG_REG_FIELD_SSCGBYP, 0x0);
> > +
> > +	writel(val, data->regs + PLLDIG_REG_PLLFM); }
> > +
> > +static int plldig_is_enabled(struct clk_hw *hw) {
> > +	struct clk_plldig *data = to_clk_plldig(hw);
> > +
> > +	return (readl(data->regs + PLLDIG_REG_PLLFM) &
> > +			      PLLDIG_REG_FIELD_SSCGBYP);
> > +}
> > +
> > +static unsigned long plldig_recalc_rate(struct clk_hw *hw,
> > +		unsigned long parent_rate)
> > +{
> > +	struct clk_plldig *data = to_clk_plldig(hw);
> > +	u32 mult, div, val;
> > +
> > +	val = readl(data->regs + PLLDIG_REG_PLLDV);
> > +
> > +	/* Check if PLL is bypassed */
> > +	if (val & PLLDIG_REG_FIELD_SSCGBYP)
> > +		return parent_rate;
> > +
> > +	/* Checkout multiplication factor divider value */
> > +	mult = FIELD_GET(PLLDIG_REG_FIELD_MULT, val);
> > +
> > +	/* Checkout divider value of the output frequency */
> > +	div = FIELD_GET(PLLDIG_REG_FIELD_RFDPHI1, val);
> > +
> > +	return (parent_rate * mult) / div;
> > +}
> > +
> > +static int plldig_calc_target_rate(unsigned long target_rate,
> > +				   unsigned long parent_rate,
> > +				   struct plldig_phi1_param *phi1) {
> > +	unsigned int div, ret;
> > +	unsigned long round_rate;
> > +
> > +	/* Range limitation of the request target rate */
> > +	if (target_rate > PHI1_MAX_FREQ)
> > +		target_rate = PHI1_MAX_FREQ;
> > +	else if (target_rate < PHI1_MIN_FREQ)
> > +		target_rate = PHI1_MIN_FREQ;
> > +
> > +	/*
> > +	 * Firstly, check the request target rate whether is divisible
> > +	 * by the best VCO frequency.
> > +	 */
> > +	round_rate = parent_rate * phi1->mfd;
> > +	div = round_rate / target_rate;
> > +	if (!div || div > MAX_RFDPHI1)
> > +		return -EINVAL;
> > +
> > +	ret = round_rate % target_rate;
> > +	if (ret) {
> > +		/*
> > +		 * Rounded down the request target rate, VESA specifies
> > +		 * 0.5% pixel clock tolerance, therefore this algorithm
> > +		 * can able to compatible a lot of request rates within
> > +		 * range of the tolerance.
> > +		 */
> > +		round_rate += (target_rate / 2);
> > +		div = round_rate / target_rate;
> > +		if (!div || div > MAX_RFDPHI1)
> > +			return -EINVAL;
> > +	}
> > +
> > +	phi1->rfdphi1 = div;
> > +	phi1->rate = target_rate;
> > +
> > +	return 0;
> > +}
> > +
> > +static int plldig_determine_rate(struct clk_hw *hw,
> > +				 struct clk_rate_request *req)
> > +{
> > +	int ret;
> > +	unsigned long parent_rate;
> > +	struct clk_hw *parent;
> > +	struct plldig_phi1_param phi1_param;
> > +	struct clk_plldig *data = to_clk_plldig(hw);
> > +
> > +	if (!req->rate)
> > +		return -ERANGE;
> > +
> > +	phi1_param.mfd = data->mfd;
> > +	parent = clk_hw_get_parent(hw);
> > +	parent_rate = clk_hw_get_rate(parent);
> > +
> > +	ret = plldig_calc_target_rate(req->rate, parent_rate, &phi1_param);
> > +	if (ret)
> > +		return ret;
> > +
> > +	req->rate = phi1_param.rate;
> > +
> > +	return 0;
> > +}
> > +
> > +static int plldig_set_rate(struct clk_hw *hw, unsigned long rate,
> > +		unsigned long parent_rate)
> > +{
> > +	struct clk_plldig *data = to_clk_plldig(hw);
> > +	struct plldig_phi1_param phi1_param;
> > +	unsigned int val, cond;
> > +	int ret;
> > +
> > +	ret = plldig_calc_target_rate(rate, parent_rate, &phi1_param);
> > +	if (ret)
> > +		return ret;
> > +
> > +	val = readl(data->regs + PLLDIG_REG_PLLDV);
> > +	val = FIELD_PREP(PLLDIG_REG_FIELD_MULT, data->mfd) |
> > +	      FIELD_PREP(PLLDIG_REG_FIELD_RFDPHI1, phi1_param.rfdphi1);
> > +
> > +	writel(val, data->regs + PLLDIG_REG_PLLDV);
> > +
> > +	/* delay 200us make sure that old lock state is cleared */
> > +	udelay(200);
> > +
> > +	/* Wait until PLL is locked or timeout (maximum 1000 usecs) */
> > +	return readl_poll_timeout_atomic(data->regs + PLLDIG_REG_PLLSR,
> > cond,
> > +					 cond & PLLDIG_LOCK_MASK, 0,
> > +					 USEC_PER_MSEC);
> > +}
> > +
> > +static const struct clk_ops plldig_clk_ops = {
> > +	.enable = plldig_enable,
> > +	.disable = plldig_disable,
> > +	.is_enabled = plldig_is_enabled,
> > +	.recalc_rate = plldig_recalc_rate,
> > +	.determine_rate = plldig_determine_rate,
> > +	.set_rate = plldig_set_rate,
> > +};
> > +
> > +static int plldig_clk_probe(struct platform_device *pdev) {
> > +	struct clk_plldig *data;
> > +	struct resource *mem;
> > +	struct device *dev = &pdev->dev;
> > +	int ret;
> > +
> > +	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
> > +	if (!data)
> > +		return -ENOMEM;
> > +
> > +	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > +	data->regs = devm_ioremap_resource(dev, mem);
> > +	if (IS_ERR(data->regs))
> > +		return PTR_ERR(data->regs);
> > +
> > +	 /*
> > +	  * Support to get the best loop multiplication divider value
> > +	  * from DTS file, since this PLL can't changed this value on
> > +	  * the fly, write the fixed value.
> > +	  */
> > +	ret = of_property_read_u32(dev->of_node, "best-mfd", &data-
> > >mfd);
> > +	if (ret)
> > +		data->mfd = 0x2c;
> > +
> > +	data->hw.init = CLK_HW_INIT_PARENTS_DATA("dpclk",
> > +						 parent_data,
> > +						 &plldig_clk_ops,
> > +						 0);
> > +
> > +	ret = devm_clk_hw_register(dev, &data->hw);
> > +	if (ret) {
> > +		dev_err(dev, "failed to register %s clock\n",
> > +						dev->of_node->name);
> > +		return ret;
> > +	}
> > +
> > +	return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
> > +					   &data->hw);
> > +}
> > +
> > +static const struct of_device_id plldig_clk_id[] = {
> > +	{ .compatible = "fsl,ls1028a-plldig"},
> > +	{ }
> > +};
> > +MODULE_DEVICE_TABLE(of, plldig_clk_id);
> > +
> > +static struct platform_driver plldig_clk_driver = {
> > +	.driver = {
> > +		.name = "plldig-clock",
> > +		.of_match_table = plldig_clk_id,
> > +	},
> > +	.probe = plldig_clk_probe,
> > +};
> > +module_platform_driver(plldig_clk_driver);
> > +
> > +MODULE_LICENSE("GPL v2");
> > +MODULE_AUTHOR("Wen He <wen.he_1@nxp.com>");
> > MODULE_DESCRIPTION("LS1028A
> > +Display output interface pixel clock driver");
> > --
> > 2.17.1
Stephen Boyd Nov. 7, 2019, 10:57 p.m. UTC | #3 
Quoting Wen He (2019-11-06 19:13:48)
> 
> > > diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index
> > > 0138fb14e6f8..d23b7464aba8 100644
> > > --- a/drivers/clk/Makefile
> > > +++ b/drivers/clk/Makefile
> > > @@ -45,6 +45,7 @@ obj-$(CONFIG_COMMON_CLK_OXNAS)            +=
> > > clk-oxnas.o
> > >  obj-$(CONFIG_COMMON_CLK_PALMAS)            += clk-palmas.o
> > >  obj-$(CONFIG_COMMON_CLK_PWM)               += clk-pwm.o
> > >  obj-$(CONFIG_CLK_QORIQ)                    += clk-qoriq.o
> > > +obj-$(CONFIG_CLK_LS1028A_PLLDIG)   += clk-plldig.o
> > 
> > Wrong ordering.  This section of Makefile requires ordering by driver file
> > name:
> > 
> > # hardware specific clock types
> > # please keep this section sorted lexicographically by file path name
> > 
> 
> Hi Leo,
> 
> Stephen once suggest the Kconfig variable name should be given a more
> specific name like CLK_LS1028A_PLLDIG, so I have to changed it.
> 
> Hi Stephen,
> 
> How do you think?
> 


Config name looks fine to me, but you haven't sorted this based on the
file name, i.e. clk-plldig.o, so please insert this in the right place
in this file.
Wen He Nov. 8, 2019, 2:19 a.m. UTC | #4 
> -----Original Message-----
> From: Stephen Boyd <sboyd@kernel.org>
> Sent: 2019年11月8日 6:58
> To: Leo Li <leoyang.li@nxp.com>; Mark Rutland <mark.rutland@arm.com>;
> Michael Turquette <mturquette@baylibre.com>; Rob Herring
> <robh+dt@kernel.org>; Wen He <wen.he_1@nxp.com>;
> devicetree@vger.kernel.org; linux-clk@vger.kernel.org;
> linux-devel@linux.nxdi.nxp.com; linux-kernel@vger.kernel.org
> Subject: [EXT] RE: [v6 2/2] clk: ls1028a: Add clock driver for Display output
> interface
> 
> Caution: EXT Email
> 
> Quoting Wen He (2019-11-06 19:13:48)
> >
> > > > diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index
> > > > 0138fb14e6f8..d23b7464aba8 100644
> > > > --- a/drivers/clk/Makefile
> > > > +++ b/drivers/clk/Makefile
> > > > @@ -45,6 +45,7 @@ obj-$(CONFIG_COMMON_CLK_OXNAS)
> +=
> > > > clk-oxnas.o
> > > >  obj-$(CONFIG_COMMON_CLK_PALMAS)            += clk-palmas.o
> > > >  obj-$(CONFIG_COMMON_CLK_PWM)               += clk-pwm.o
> > > >  obj-$(CONFIG_CLK_QORIQ)                    += clk-qoriq.o
> > > > +obj-$(CONFIG_CLK_LS1028A_PLLDIG)   += clk-plldig.o
> > >
> > > Wrong ordering.  This section of Makefile requires ordering by
> > > driver file
> > > name:
> > >
> > > # hardware specific clock types
> > > # please keep this section sorted lexicographically by file path
> > > name
> > >
> >
> > Hi Leo,
> >
> > Stephen once suggest the Kconfig variable name should be given a more
> > specific name like CLK_LS1028A_PLLDIG, so I have to changed it.
> >
> > Hi Stephen,
> >
> > How do you think?
> >
> 
> 
> Config name looks fine to me, but you haven't sorted this based on the file
> name, i.e. clk-plldig.o, so please insert this in the right place in this file.

Wow, Understand now.. 

Should be sort this file like below, right?
obj-$(CONFIG_COMMON_CLK_PWM)   += clk-pwm.o
obj-$(CONFIG_CLK_LS1028A_PLLDIG)   += clk-plldig.o
obj-$(CONFIG_CLK_QORIQ)           += clk-qoriq.o

Best Regards,
Wen
Leo Li Nov. 8, 2019, 8:20 p.m. UTC | #5 
On Thu, Nov 7, 2019 at 8:21 PM Wen He <wen.he_1@nxp.com> wrote:
>
>
>
> > -----Original Message-----
> > From: Stephen Boyd <sboyd@kernel.org>
> > Sent: 2019年11月8日 6:58
> > To: Leo Li <leoyang.li@nxp.com>; Mark Rutland <mark.rutland@arm.com>;
> > Michael Turquette <mturquette@baylibre.com>; Rob Herring
> > <robh+dt@kernel.org>; Wen He <wen.he_1@nxp.com>;
> > devicetree@vger.kernel.org; linux-clk@vger.kernel.org;
> > linux-devel@linux.nxdi.nxp.com; linux-kernel@vger.kernel.org
> > Subject: [EXT] RE: [v6 2/2] clk: ls1028a: Add clock driver for Display output
> > interface
> >
> > Caution: EXT Email
> >
> > Quoting Wen He (2019-11-06 19:13:48)
> > >
> > > > > diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index
> > > > > 0138fb14e6f8..d23b7464aba8 100644
> > > > > --- a/drivers/clk/Makefile
> > > > > +++ b/drivers/clk/Makefile
> > > > > @@ -45,6 +45,7 @@ obj-$(CONFIG_COMMON_CLK_OXNAS)
> > +=
> > > > > clk-oxnas.o
> > > > >  obj-$(CONFIG_COMMON_CLK_PALMAS)            += clk-palmas.o
> > > > >  obj-$(CONFIG_COMMON_CLK_PWM)               += clk-pwm.o
> > > > >  obj-$(CONFIG_CLK_QORIQ)                    += clk-qoriq.o
> > > > > +obj-$(CONFIG_CLK_LS1028A_PLLDIG)   += clk-plldig.o
> > > >
> > > > Wrong ordering.  This section of Makefile requires ordering by
> > > > driver file
> > > > name:
> > > >
> > > > # hardware specific clock types
> > > > # please keep this section sorted lexicographically by file path
> > > > name
> > > >
> > >
> > > Hi Leo,
> > >
> > > Stephen once suggest the Kconfig variable name should be given a more
> > > specific name like CLK_LS1028A_PLLDIG, so I have to changed it.
> > >
> > > Hi Stephen,
> > >
> > > How do you think?
> > >
> >
> >
> > Config name looks fine to me, but you haven't sorted this based on the file
> > name, i.e. clk-plldig.o, so please insert this in the right place in this file.
>
> Wow, Understand now..
>
> Should be sort this file like below, right?
> obj-$(CONFIG_COMMON_CLK_PWM)   += clk-pwm.o
> obj-$(CONFIG_CLK_LS1028A_PLLDIG)   += clk-plldig.o
> obj-$(CONFIG_CLK_QORIQ)           += clk-qoriq.o

No.  The correct order should be:
clk-plldig.o
clk-pwm.o
clk-qoriq.o

Regards,
Leo
Wen He Nov. 11, 2019, 2:02 a.m. UTC | #6 
> -----Original Message-----
> From: Li Yang <leoyang.li@nxp.com>
> Sent: 2019年11月9日 4:20
> To: Wen He <wen.he_1@nxp.com>
> Cc: Stephen Boyd <sboyd@kernel.org>; Mark Rutland
> <mark.rutland@arm.com>; Michael Turquette <mturquette@baylibre.com>;
> Rob Herring <robh+dt@kernel.org>; devicetree@vger.kernel.org;
> linux-clk@vger.kernel.org; linux-devel@linux.nxdi.nxp.com;
> linux-kernel@vger.kernel.org
> Subject: Re: [EXT] RE: [v6 2/2] clk: ls1028a: Add clock driver for Display output
> interface
> 
> Caution: EXT Email
> 
> On Thu, Nov 7, 2019 at 8:21 PM Wen He <wen.he_1@nxp.com> wrote:
> >
> >
> >
> > > -----Original Message-----
> > > From: Stephen Boyd <sboyd@kernel.org>
> > > Sent: 2019年11月8日 6:58
> > > To: Leo Li <leoyang.li@nxp.com>; Mark Rutland
> > > <mark.rutland@arm.com>; Michael Turquette
> <mturquette@baylibre.com>;
> > > Rob Herring <robh+dt@kernel.org>; Wen He <wen.he_1@nxp.com>;
> > > devicetree@vger.kernel.org; linux-clk@vger.kernel.org;
> > > linux-devel@linux.nxdi.nxp.com; linux-kernel@vger.kernel.org
> > > Subject: [EXT] RE: [v6 2/2] clk: ls1028a: Add clock driver for
> > > Display output interface
> > >
> > > Caution: EXT Email
> > >
> > > Quoting Wen He (2019-11-06 19:13:48)
> > > >
> > > > > > diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index
> > > > > > 0138fb14e6f8..d23b7464aba8 100644
> > > > > > --- a/drivers/clk/Makefile
> > > > > > +++ b/drivers/clk/Makefile
> > > > > > @@ -45,6 +45,7 @@ obj-$(CONFIG_COMMON_CLK_OXNAS)
> > > +=
> > > > > > clk-oxnas.o
> > > > > >  obj-$(CONFIG_COMMON_CLK_PALMAS)            +=
> clk-palmas.o
> > > > > >  obj-$(CONFIG_COMMON_CLK_PWM)               +=
> clk-pwm.o
> > > > > >  obj-$(CONFIG_CLK_QORIQ)                    += clk-qoriq.o
> > > > > > +obj-$(CONFIG_CLK_LS1028A_PLLDIG)   += clk-plldig.o
> > > > >
> > > > > Wrong ordering.  This section of Makefile requires ordering by
> > > > > driver file
> > > > > name:
> > > > >
> > > > > # hardware specific clock types
> > > > > # please keep this section sorted lexicographically by file path
> > > > > name
> > > > >
> > > >
> > > > Hi Leo,
> > > >
> > > > Stephen once suggest the Kconfig variable name should be given a
> > > > more specific name like CLK_LS1028A_PLLDIG, so I have to changed it.
> > > >
> > > > Hi Stephen,
> > > >
> > > > How do you think?
> > > >
> > >
> > >
> > > Config name looks fine to me, but you haven't sorted this based on
> > > the file name, i.e. clk-plldig.o, so please insert this in the right place in this
> file.
> >
> > Wow, Understand now..
> >
> > Should be sort this file like below, right?
> > obj-$(CONFIG_COMMON_CLK_PWM)   += clk-pwm.o
> > obj-$(CONFIG_CLK_LS1028A_PLLDIG)   += clk-plldig.o
> > obj-$(CONFIG_CLK_QORIQ)           += clk-qoriq.o
> 
> No.  The correct order should be:
> clk-plldig.o
> clk-pwm.o
> clk-qoriq.o

Understand, I will send next version patch.

Thanks && Best Regards,
Wen

> 
> Regards,
> Leo
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/clock/fsl,plldig.yaml b/Documentation/devicetree/bindings/clock/fsl,plldig.yaml
new file mode 100644
index 000000000000..32274e94aafc
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/fsl,plldig.yaml
@@ -0,0 +1,43 @@ 
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bindings/clock/fsl,plldig.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP QorIQ Layerscape LS1028A Display PIXEL Clock Binding
+
+maintainers:
+  - Wen He <wen.he_1@nxp.com>
+
+description: |
+  NXP LS1028A has a clock domain PXLCLK0 used for the Display output
+  interface in the display core, as implemented in TSMC CLN28HPM PLL.
+  which generate and offers pixel clocks to Display.
+
+properties:
+  compatible:
+    const: fsl,ls1028a-plldig
+
+  reg:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 0
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - '#clock-cells'
+
+examples:
+  # Display PIXEL Clock node:
+  - |
+    dpclk: clock-display@f1f0000 {
+        compatible = "fsl,ls1028a-plldig";
+        reg = <0x0 0xf1f0000 0x0 0xffff>;
+        #clock-cells = <0>;
+        clocks = <&osc_27m>;
+    };
+
+...