@@ -32,6 +32,7 @@
#define CSD0_BASE_ADDR 0x90000000
#define CSD1_BASE_ADDR 0xA0000000
#define NFC_BASE_ADDR_AXI 0xCFFF0000
+#define CS1_BASE_ADDR 0xB8000000
#elif defined(CONFIG_MX53)
#define IPU_CTRL_BASE_ADDR 0x18000000
#define SPBA0_BASE_ADDR 0x50000000
@@ -41,6 +42,7 @@
#define CSD1_BASE_ADDR 0xB0000000
#define NFC_BASE_ADDR_AXI 0xF7FF0000
#define IRAM_BASE_ADDR 0xF8000000
+#define CS1_BASE_ADDR 0xF4000000
#else
#error "CPU_TYPE not defined"
#endif
@@ -129,6 +131,90 @@
#define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000)
/*
+ * WEIM CSnGCR1
+ */
+#define CSEN 1
+#define SWR (1 << 1)
+#define SRD (1 << 2)
+#define MUM (1 << 3)
+#define WFL (1 << 4)
+#define RFL (1 << 5)
+#define CRE (1 << 6)
+#define CREP (1 << 7)
+#define BL(x) (((x) & 0x7) << 8)
+#define WC (1 << 11)
+#define BCD(x) (((x) & 0x3) << 12)
+#define BCS(x) (((x) & 0x3) << 14)
+#define DSZ(x) (((x) & 0x7) << 16)
+#define SP (1 << 19)
+#define CSREC(x) (((x) & 0x7) << 20)
+#define AUS (1 << 23)
+#define GBC(x) (((x) & 0x7) << 24)
+#define WP (1 << 27)
+#define PSZ(x) (((x) & 0x0f << 28)
+
+/*
+ * WEIM CSnGCR2
+ */
+#define ADH(x) (((x) & 0x3))
+#define DAPS(x) (((x) & 0x0f << 4)
+#define DAE (1 << 8)
+#define DAP (1 << 9)
+#define MUX16_BYP (1 << 12)
+
+/*
+ * WEIM CSnRCR1
+ */
+#define RCSN(x) (((x) & 0x7))
+#define RCSA(x) (((x) & 0x7) << 4)
+#define OEN(x) (((x) & 0x7) << 8)
+#define OEA(x) (((x) & 0x7) << 12)
+#define RADVN(x) (((x) & 0x7) << 16)
+#define RAL (1 << 19)
+#define RADVA(x) (((x) & 0x7) << 20)
+#define RWSC(x) (((x) & 0x3f) << 24)
+
+/*
+ * WEIM CSnRCR2
+ */
+#define RBEN(x) (((x) & 0x7))
+#define RBE (1 << 3)
+#define RBEA(x) (((x) & 0x7) << 4)
+#define RL(x) (((x) & 0x3) << 8)
+#define PAT(x) (((x) & 0x7) << 12)
+#define APR (1 << 15)
+
+/*
+ * WEIM CSnWCR1
+ */
+#define WCSN(x) (((x) & 0x7))
+#define WCSA(x) (((x) & 0x7) << 3)
+#define WEN(x) (((x) & 0x7) << 6)
+#define WEA(x) (((x) & 0x7) << 9)
+#define WBEN(x) (((x) & 0x7) << 12)
+#define WBEA(x) (((x) & 0x7) << 15)
+#define WADVN(x) (((x) & 0x7) << 18)
+#define WADVA(x) (((x) & 0x7) << 21)
+#define WWSC(x) (((x) & 0x3f) << 24)
+#define WBED1 (1 << 30)
+#define WAL (1 << 31)
+
+/*
+ * WEIM CSnWCR2
+ */
+#define WBED 1
+
+/*
+ * WEIM WCR
+ */
+#define BCM 1
+#define GBCD(x) (((x) & 0x3) << 1)
+#define INTEN (1 << 4)
+#define INTPOL (1 << 5)
+#define WDOG_EN (1 << 8)
+#define WDOG_LIMIT(x) (((x) & 0x3) << 9)
+
+/*
* Number of GPIO pins per port
*/
#define GPIO_NUM_PIN 32
@@ -231,12 +317,45 @@ struct clkctl {
/* WEIM registers */
struct weim {
- u32 csgcr1;
- u32 csgcr2;
- u32 csrcr1;
- u32 csrcr2;
- u32 cswcr1;
- u32 cswcr2;
+ u32 cs0gcr1;
+ u32 cs0gcr2;
+ u32 cs0rcr1;
+ u32 cs0rcr2;
+ u32 cs0wcr1;
+ u32 cs0wcr2;
+ u32 cs1gcr1;
+ u32 cs1gcr2;
+ u32 cs1rcr1;
+ u32 cs1rcr2;
+ u32 cs1wcr1;
+ u32 cs1wcr2;
+ u32 cs2gcr1;
+ u32 cs2gcr2;
+ u32 cs2rcr1;
+ u32 cs2rcr2;
+ u32 cs2wcr1;
+ u32 cs2wcr2;
+ u32 cs3gcr1;
+ u32 cs3gcr2;
+ u32 cs3rcr1;
+ u32 cs3rcr2;
+ u32 cs3wcr1;
+ u32 cs3wcr2;
+ u32 cs4gcr1;
+ u32 cs4gcr2;
+ u32 cs4rcr1;
+ u32 cs4rcr2;
+ u32 cs4wcr1;
+ u32 cs4wcr2;
+ u32 cs5gcr1;
+ u32 cs5gcr2;
+ u32 cs5rcr1;
+ u32 cs5rcr2;
+ u32 cs5wcr1;
+ u32 cs5wcr2;
+ u32 wcr;
+ u32 wiar;
+ u32 ear;
};
/* GPIO Registers */
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> --- Changes since v4: - Change the definition of WEIM single-bit field Changes since v3: - No changes Changes since v2: - Add CS1_BASE_ADDR for MX51 - Add WEIM Registers arch/arm/include/asm/arch-mx5/imx-regs.h | 131 ++++++++++++++++++++++++++++-- 1 files changed, 125 insertions(+), 6 deletions(-)