| Message ID | 20191011075820.6596-1-vigneshr@ti.com |
|---|---|
| Headers | show |
| Series | spi-nor: spi-nor-ids: Fix 4 Byte addressing for n25q* | expand |
On Fri, Oct 11, 2019 at 1:28 PM Vignesh Raghavendra <vigneshr@ti.com> wrote: > > n25q variants do not support stateless 4 byte addressing opcodes by default, > therefore first patch disables this flag for those parts. Second patch > adds entries for mt25q variants which are similar to n25q but supports > stateless 4 byte opcodes. Third patch adds USE_FSR flag for mt25q* and > n25q* variants where missing > > Changes since v2: > Add USE_FSR flags to all flash variants where missing > Collect T-bys and R-bys > Reword commit msgs as necessary > > Changes since v1: > Rename newer variants as mt25* > Add a patch to enable flag register parsing for mt25qu512a > > Vignesh Raghavendra (3): > spi-nor: spi-nor-ids: Disable SPI_NOR_4B_OPCODES for n25q512* and > n25q256* > spi-nor: spi-nor-ids: Add entries for mt25q variants > spi-nor: spi-nor-ids: Add USE_FSR flag for mt25q* and n25q* entry Applied to u-boot-spi/master
n25q variants do not support stateless 4 byte addressing opcodes by default, therefore first patch disables this flag for those parts. Second patch adds entries for mt25q variants which are similar to n25q but supports stateless 4 byte opcodes. Third patch adds USE_FSR flag for mt25q* and n25q* variants where missing Changes since v2: Add USE_FSR flags to all flash variants where missing Collect T-bys and R-bys Reword commit msgs as necessary Changes since v1: Rename newer variants as mt25* Add a patch to enable flag register parsing for mt25qu512a Vignesh Raghavendra (3): spi-nor: spi-nor-ids: Disable SPI_NOR_4B_OPCODES for n25q512* and n25q256* spi-nor: spi-nor-ids: Add entries for mt25q variants spi-nor: spi-nor-ids: Add USE_FSR flag for mt25q* and n25q* entry drivers/mtd/spi/spi-nor-ids.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-)