Message ID | d0a6c68c4af8e3f160cce19fea8bbd9f20aea0be.1566603412.git.alistair.francis@wdc.com |
---|---|
State | New |
Headers | show |
Series | Add RISC-V Hypervisor Extension v0.4 | expand |
On Fri, 23 Aug 2019 16:38:36 PDT (-0700), Alistair Francis wrote: > Signed-off-by: Alistair Francis <alistair.francis@wdc.com> > --- > target/riscv/insn32.decode | 23 ++++++----- > .../riscv/insn_trans/trans_privileged.inc.c | 40 +++++++++++++++++++ > 2 files changed, 54 insertions(+), 9 deletions(-) > > diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode > index 77f794ed70..cfd9ca6d2b 100644 > --- a/target/riscv/insn32.decode > +++ b/target/riscv/insn32.decode > @@ -63,20 +63,25 @@ > @r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd > @r2 ....... ..... ..... ... ..... ....... %rs1 %rd > > +@hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1 > +@hfence_bvma ....... ..... ..... ... ..... ....... %rs2 %rs1 > + > @sfence_vma ....... ..... ..... ... ..... ....... %rs2 %rs1 > @sfence_vm ....... ..... ..... ... ..... ....... %rs1 > > > # *** Privileged Instructions *** > -ecall 000000000000 00000 000 00000 1110011 > -ebreak 000000000001 00000 000 00000 1110011 > -uret 0000000 00010 00000 000 00000 1110011 > -sret 0001000 00010 00000 000 00000 1110011 > -hret 0010000 00010 00000 000 00000 1110011 > -mret 0011000 00010 00000 000 00000 1110011 > -wfi 0001000 00101 00000 000 00000 1110011 > -sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma > -sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm > +ecall 000000000000 00000 000 00000 1110011 > +ebreak 000000000001 00000 000 00000 1110011 > +uret 0000000 00010 00000 000 00000 1110011 > +sret 0001000 00010 00000 000 00000 1110011 > +hret 0010000 00010 00000 000 00000 1110011 > +mret 0011000 00010 00000 000 00000 1110011 > +wfi 0001000 00101 00000 000 00000 1110011 > +hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma > +hfence_bvma 0010001 ..... ..... 000 00000 1110011 @hfence_bvma > +sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma > +sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm > > # *** RV32I Base Instruction Set *** > lui .................... ..... 0110111 @u > diff --git a/target/riscv/insn_trans/trans_privileged.inc.c b/target/riscv/insn_trans/trans_privileged.inc.c > index c5e4b3e49a..b9b5a89b52 100644 > --- a/target/riscv/insn_trans/trans_privileged.inc.c > +++ b/target/riscv/insn_trans/trans_privileged.inc.c > @@ -108,3 +108,43 @@ static bool trans_sfence_vm(DisasContext *ctx, arg_sfence_vm *a) > #endif > return false; > } > + > +static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a) > +{ > +#ifndef CONFIG_USER_ONLY > + if (ctx->priv_ver >= PRIV_VERSION_1_10_0 && > + has_ext(ctx, RVH)) { > + /* Hpervisor extensions exist */ > + /* > + * if (env->priv == PRV_M || > + * (env->priv == PRV_S && > + * !riscv_cpu_virt_enabled(env) && > + * get_field(ctx->mstatus_fs, MSTATUS_TVM))) { > + */ > + gen_helper_tlb_flush(cpu_env); > + return true; > + /* } */ > + } > +#endif > + return false; > +} > + > +static bool trans_hfence_bvma(DisasContext *ctx, arg_sfence_vma *a) > +{ > +#ifndef CONFIG_USER_ONLY > + if (ctx->priv_ver >= PRIV_VERSION_1_10_0 && > + has_ext(ctx, RVH)) { > + /* Hpervisor extensions exist */ > + /* > + * if (env->priv == PRV_M || > + * (env->priv == PRV_S && > + * !riscv_cpu_virt_enabled(env) && > + * get_field(ctx->mstatus_fs, MSTATUS_TVM))) { > + */ > + gen_helper_tlb_flush(cpu_env); > + return true; > + /* } */ > + } > +#endif > + return false; > +} Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 77f794ed70..cfd9ca6d2b 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -63,20 +63,25 @@ @r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd @r2 ....... ..... ..... ... ..... ....... %rs1 %rd +@hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1 +@hfence_bvma ....... ..... ..... ... ..... ....... %rs2 %rs1 + @sfence_vma ....... ..... ..... ... ..... ....... %rs2 %rs1 @sfence_vm ....... ..... ..... ... ..... ....... %rs1 # *** Privileged Instructions *** -ecall 000000000000 00000 000 00000 1110011 -ebreak 000000000001 00000 000 00000 1110011 -uret 0000000 00010 00000 000 00000 1110011 -sret 0001000 00010 00000 000 00000 1110011 -hret 0010000 00010 00000 000 00000 1110011 -mret 0011000 00010 00000 000 00000 1110011 -wfi 0001000 00101 00000 000 00000 1110011 -sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma -sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm +ecall 000000000000 00000 000 00000 1110011 +ebreak 000000000001 00000 000 00000 1110011 +uret 0000000 00010 00000 000 00000 1110011 +sret 0001000 00010 00000 000 00000 1110011 +hret 0010000 00010 00000 000 00000 1110011 +mret 0011000 00010 00000 000 00000 1110011 +wfi 0001000 00101 00000 000 00000 1110011 +hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma +hfence_bvma 0010001 ..... ..... 000 00000 1110011 @hfence_bvma +sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma +sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm # *** RV32I Base Instruction Set *** lui .................... ..... 0110111 @u diff --git a/target/riscv/insn_trans/trans_privileged.inc.c b/target/riscv/insn_trans/trans_privileged.inc.c index c5e4b3e49a..b9b5a89b52 100644 --- a/target/riscv/insn_trans/trans_privileged.inc.c +++ b/target/riscv/insn_trans/trans_privileged.inc.c @@ -108,3 +108,43 @@ static bool trans_sfence_vm(DisasContext *ctx, arg_sfence_vm *a) #endif return false; } + +static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a) +{ +#ifndef CONFIG_USER_ONLY + if (ctx->priv_ver >= PRIV_VERSION_1_10_0 && + has_ext(ctx, RVH)) { + /* Hpervisor extensions exist */ + /* + * if (env->priv == PRV_M || + * (env->priv == PRV_S && + * !riscv_cpu_virt_enabled(env) && + * get_field(ctx->mstatus_fs, MSTATUS_TVM))) { + */ + gen_helper_tlb_flush(cpu_env); + return true; + /* } */ + } +#endif + return false; +} + +static bool trans_hfence_bvma(DisasContext *ctx, arg_sfence_vma *a) +{ +#ifndef CONFIG_USER_ONLY + if (ctx->priv_ver >= PRIV_VERSION_1_10_0 && + has_ext(ctx, RVH)) { + /* Hpervisor extensions exist */ + /* + * if (env->priv == PRV_M || + * (env->priv == PRV_S && + * !riscv_cpu_virt_enabled(env) && + * get_field(ctx->mstatus_fs, MSTATUS_TVM))) { + */ + gen_helper_tlb_flush(cpu_env); + return true; + /* } */ + } +#endif + return false; +}
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> --- target/riscv/insn32.decode | 23 ++++++----- .../riscv/insn_trans/trans_privileged.inc.c | 40 +++++++++++++++++++ 2 files changed, 54 insertions(+), 9 deletions(-)