| Message ID | 331759c1bcba5797d30f8eace74afb16ac5f3c36.1566564560.git.christophe.leroy@c-s.fr (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [1/2] powerpc/32s: automatically allocate BAT in setbat() | expand |
| Context | Check | Description |
|---|---|---|
| snowpatch_ozlabs/apply_patch | success | Successfully applied on branch next (0e4523c0b4f64eaf7abe59e143e6bdf8f972acff) |
| snowpatch_ozlabs/build-ppc64le | success | Build succeeded |
| snowpatch_ozlabs/build-ppc64be | success | Build succeeded |
| snowpatch_ozlabs/build-ppc64e | success | Build succeeded |
| snowpatch_ozlabs/build-pmac32 | success | Build succeeded |
| snowpatch_ozlabs/checkpatch | success | total: 0 errors, 0 warnings, 0 checks, 22 lines checked |
On Fri, 2019-08-23 at 12:50 +0000, Christophe Leroy wrote: > On mpc83xx with a QE, IMMR is 2Mbytes. > On mpc83xx without a QE, IMMR is 1Mbytes. > Each driver will map a part of it to access the registers it needs. > Some driver will map the same part of IMMR as other drivers. > > In order to reduce TLB misses, map the full IMMR with a BAT. > > Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> > --- > arch/powerpc/platforms/83xx/misc.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/arch/powerpc/platforms/83xx/misc.c > b/arch/powerpc/platforms/83xx/misc.c > index f46d7bf3b140..1e395b01c535 100644 > --- a/arch/powerpc/platforms/83xx/misc.c > +++ b/arch/powerpc/platforms/83xx/misc.c > @@ -18,6 +18,8 @@ > #include <sysdev/fsl_soc.h> > #include <sysdev/fsl_pci.h> > > +#include <mm/mmu_decl.h> > + > #include "mpc83xx.h" > > static __be32 __iomem *restart_reg_base; > @@ -145,6 +147,14 @@ void __init mpc83xx_setup_arch(void) > if (ppc_md.progress) > ppc_md.progress("mpc83xx_setup_arch()", 0); > > + if (!__map_without_bats) { > + int immrsize = IS_ENABLED(CONFIG_QUICC_ENGINE) ? SZ_2M : > SZ_1M; Any reason not to unconditionally make it 2M? After all, the kernel being built with CONFIG_QUICC_ENGINE doesn't mean that the hardware you're running on has it... -Scott
Le 14/09/2019 à 16:34, Scott Wood a écrit : > On Fri, 2019-08-23 at 12:50 +0000, Christophe Leroy wrote: >> On mpc83xx with a QE, IMMR is 2Mbytes. >> On mpc83xx without a QE, IMMR is 1Mbytes. >> Each driver will map a part of it to access the registers it needs. >> Some driver will map the same part of IMMR as other drivers. >> >> In order to reduce TLB misses, map the full IMMR with a BAT. >> >> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> >> --- >> arch/powerpc/platforms/83xx/misc.c | 10 ++++++++++ >> 1 file changed, 10 insertions(+) >> >> diff --git a/arch/powerpc/platforms/83xx/misc.c >> b/arch/powerpc/platforms/83xx/misc.c >> index f46d7bf3b140..1e395b01c535 100644 >> --- a/arch/powerpc/platforms/83xx/misc.c >> +++ b/arch/powerpc/platforms/83xx/misc.c >> @@ -18,6 +18,8 @@ >> #include <sysdev/fsl_soc.h> >> #include <sysdev/fsl_pci.h> >> >> +#include <mm/mmu_decl.h> >> + >> #include "mpc83xx.h" >> >> static __be32 __iomem *restart_reg_base; >> @@ -145,6 +147,14 @@ void __init mpc83xx_setup_arch(void) >> if (ppc_md.progress) >> ppc_md.progress("mpc83xx_setup_arch()", 0); >> >> + if (!__map_without_bats) { >> + int immrsize = IS_ENABLED(CONFIG_QUICC_ENGINE) ? SZ_2M : >> SZ_1M; > > Any reason not to unconditionally make it 2M? After all, the kernel being > built with CONFIG_QUICC_ENGINE doesn't mean that the hardware you're running > on has it... > Euh .. ok. I didn't see it that way, but you are right. Do you think it is not a problem to map 2M even when the quicc engine is not there ? Or should it check device tree instead ? Christophe
On Sat, 2019-09-14 at 18:51 +0200, Christophe Leroy wrote: > > Le 14/09/2019 à 16:34, Scott Wood a écrit : > > On Fri, 2019-08-23 at 12:50 +0000, Christophe Leroy wrote: > > > On mpc83xx with a QE, IMMR is 2Mbytes. > > > On mpc83xx without a QE, IMMR is 1Mbytes. > > > Each driver will map a part of it to access the registers it needs. > > > Some driver will map the same part of IMMR as other drivers. > > > > > > In order to reduce TLB misses, map the full IMMR with a BAT. > > > > > > Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> > > > --- > > > arch/powerpc/platforms/83xx/misc.c | 10 ++++++++++ > > > 1 file changed, 10 insertions(+) > > > > > > diff --git a/arch/powerpc/platforms/83xx/misc.c > > > b/arch/powerpc/platforms/83xx/misc.c > > > index f46d7bf3b140..1e395b01c535 100644 > > > --- a/arch/powerpc/platforms/83xx/misc.c > > > +++ b/arch/powerpc/platforms/83xx/misc.c > > > @@ -18,6 +18,8 @@ > > > #include <sysdev/fsl_soc.h> > > > #include <sysdev/fsl_pci.h> > > > > > > +#include <mm/mmu_decl.h> > > > + > > > #include "mpc83xx.h" > > > > > > static __be32 __iomem *restart_reg_base; > > > @@ -145,6 +147,14 @@ void __init mpc83xx_setup_arch(void) > > > if (ppc_md.progress) > > > ppc_md.progress("mpc83xx_setup_arch()", 0); > > > > > > + if (!__map_without_bats) { > > > + int immrsize = IS_ENABLED(CONFIG_QUICC_ENGINE) ? SZ_2M : > > > SZ_1M; > > > > Any reason not to unconditionally make it 2M? After all, the kernel being > > built with CONFIG_QUICC_ENGINE doesn't mean that the hardware you're > > running > > on has it... > > > > Euh .. ok. I didn't see it that way, but you are right. > > Do you think it is not a problem to map 2M even when the quicc engine is > not there ? Or should it check device tree instead ? It should be OK, since it's a guarded mapping. Unless the IMMR base is not 2M aligned... -Scott
diff --git a/arch/powerpc/platforms/83xx/misc.c b/arch/powerpc/platforms/83xx/misc.c index f46d7bf3b140..1e395b01c535 100644 --- a/arch/powerpc/platforms/83xx/misc.c +++ b/arch/powerpc/platforms/83xx/misc.c @@ -18,6 +18,8 @@ #include <sysdev/fsl_soc.h> #include <sysdev/fsl_pci.h> +#include <mm/mmu_decl.h> + #include "mpc83xx.h" static __be32 __iomem *restart_reg_base; @@ -145,6 +147,14 @@ void __init mpc83xx_setup_arch(void) if (ppc_md.progress) ppc_md.progress("mpc83xx_setup_arch()", 0); + if (!__map_without_bats) { + int immrsize = IS_ENABLED(CONFIG_QUICC_ENGINE) ? SZ_2M : SZ_1M; + + ioremap_bot = ALIGN_DOWN(ioremap_bot - immrsize, immrsize); + setbat(-1, ioremap_bot, get_immrbase(), immrsize, PAGE_KERNEL_NCG); + update_bats(); + } + mpc83xx_setup_pci(); }
On mpc83xx with a QE, IMMR is 2Mbytes. On mpc83xx without a QE, IMMR is 1Mbytes. Each driver will map a part of it to access the registers it needs. Some driver will map the same part of IMMR as other drivers. In order to reduce TLB misses, map the full IMMR with a BAT. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> --- arch/powerpc/platforms/83xx/misc.c | 10 ++++++++++ 1 file changed, 10 insertions(+)