Message ID | 413539f43f6b9c120efd4c882ce7341ef3530b81.1566603412.git.alistair.francis@wdc.com |
---|---|
State | New |
Headers | show |
Series | Add RISC-V Hypervisor Extension v0.4 | expand |
On Fri, 23 Aug 2019 16:38:05 PDT (-0700), Alistair Francis wrote: > Signed-off-by: Alistair Francis <alistair.francis@wdc.com> > --- > target/riscv/translate.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index adeddb85f6..8ac72c6470 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -810,7 +810,15 @@ static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) > > static void riscv_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) > { > +#ifndef CONFIG_USER_ONLY > + RISCVCPU *rvcpu = RISCV_CPU(cpu); > + CPURISCVState *env = &rvcpu->env; > +#endif > + > qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); > +#ifndef CONFIG_USER_ONLY > + qemu_log("Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n", env->priv, env->virt); > +#endif > log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size); > } Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
diff --git a/target/riscv/translate.c b/target/riscv/translate.c index adeddb85f6..8ac72c6470 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -810,7 +810,15 @@ static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) static void riscv_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) { +#ifndef CONFIG_USER_ONLY + RISCVCPU *rvcpu = RISCV_CPU(cpu); + CPURISCVState *env = &rvcpu->env; +#endif + qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); +#ifndef CONFIG_USER_ONLY + qemu_log("Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n", env->priv, env->virt); +#endif log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size); }
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> --- target/riscv/translate.c | 8 ++++++++ 1 file changed, 8 insertions(+)