| Message ID | 62179504-50d6-49b7-9917-ce3ab53338e7@arm.com |
|---|---|
| State | New |
| Headers | show |
| Series | [AArch64] Add support for missing CPUs | expand |
Hi Dennis, On 8/21/19 10:27 AM, Dennis Zhang wrote: > Hi all, > > This patch adds '-mcpu' options for following CPUs: > Cortex-A77, Cortex-A76AE, Cortex-A65, Cortex-A65AE, and Cortex-A34. > > Related specifications are as following: > https://developer.arm.com/ip-products/processors/cortex-a > > Bootstraped/regtested for aarch64-none-linux-gnu. > > Please help to check if it's ready. > This looks ok to me but you'll need maintainer approval. Thanks, Kyrill > Many thanks! > Dennis > > gcc/ChangeLog: > > 2019-08-21 Dennis Zhang <dennis.zhang@arm.com> > > * config/aarch64/aarch64-cores.def (AARCH64_CORE): New entries > for Cortex-A77, Cortex-A76AE, Cortex-A65, Cortex-A65AE, and > Cortex-A34. > * config/aarch64/aarch64-tune.md: Regenerated. > * doc/invoke.texi: Document the new processors.
On Thu, Aug 22, 2019 at 12:03:33PM +0100, Kyrill Tkachov wrote: > Hi Dennis, > > On 8/21/19 10:27 AM, Dennis Zhang wrote: > > Hi all, > > > > This patch adds '-mcpu' options for following CPUs: > > Cortex-A77, Cortex-A76AE, Cortex-A65, Cortex-A65AE, and Cortex-A34. > > > > Related specifications are as following: > > https://developer.arm.com/ip-products/processors/cortex-a > > > > Bootstraped/regtested for aarch64-none-linux-gnu. > > > > Please help to check if it's ready. > > > This looks ok to me but you'll need maintainer approval. At this point Kyrill, I fully trust your OK without looking at the patch in any more detail... I think at Cauldron we ought to add some time during the Arm/AArch64 BoF to discuss what the community would like us to do about maintainership in AArch64. It seems clear to me that I'm just slowing you and others down now by rubberstamping your decisions. To be clear, this particular patch is OK for trunk - but I think it is time to have a conversation about how we can make this experience easier for everyone. Thanks, James > > Thanks, > > Kyrill > > > > Many thanks! > > Dennis > > > > gcc/ChangeLog: > > > > 2019-08-21 Dennis Zhang <dennis.zhang@arm.com> > > > > * config/aarch64/aarch64-cores.def (AARCH64_CORE): New entries > > for Cortex-A77, Cortex-A76AE, Cortex-A65, Cortex-A65AE, and > > Cortex-A34. > > * config/aarch64/aarch64-tune.md: Regenerated. > > * doc/invoke.texi: Document the new processors.
Hi James, On 9/2/19 6:30 PM, James Greenhalgh wrote: > On Thu, Aug 22, 2019 at 12:03:33PM +0100, Kyrill Tkachov wrote: >> Hi Dennis, >> >> On 8/21/19 10:27 AM, Dennis Zhang wrote: >>> Hi all, >>> >>> This patch adds '-mcpu' options for following CPUs: >>> Cortex-A77, Cortex-A76AE, Cortex-A65, Cortex-A65AE, and Cortex-A34. >>> >>> Related specifications are as following: >>> https://developer.arm.com/ip-products/processors/cortex-a >>> >>> Bootstraped/regtested for aarch64-none-linux-gnu. >>> >>> Please help to check if it's ready. >>> >> This looks ok to me but you'll need maintainer approval. > At this point Kyrill, I fully trust your OK without looking at the > patch in any more detail... > > I think at Cauldron we ought to add some time during the Arm/AArch64 BoF > to discuss what the community would like us to do about maintainership in > AArch64. It seems clear to me that I'm just slowing you and others down now > by rubberstamping your decisions. Ok, judging by the schedule there should be plenty of opportunity to discuss innovative maintainership schemes at Cauldron! > To be clear, this particular patch is OK for trunk - but I think it is > time to have a conversation about how we can make this experience easier > for everyone. Thanks, I've committed this on Dennis' behalf with r275333. Kyrill > Thanks, > James > >> Thanks, >> >> Kyrill >> >> >>> Many thanks! >>> Dennis >>> >>> gcc/ChangeLog: >>> >>> 2019-08-21 Dennis Zhang <dennis.zhang@arm.com> >>> >>> * config/aarch64/aarch64-cores.def (AARCH64_CORE): New entries >>> for Cortex-A77, Cortex-A76AE, Cortex-A65, Cortex-A65AE, and >>> Cortex-A34. >>> * config/aarch64/aarch64-tune.md: Regenerated. >>> * doc/invoke.texi: Document the new processors.
diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def index 82d91d62519..c0be109009f 100644 --- a/gcc/config/aarch64/aarch64-cores.def +++ b/gcc/config/aarch64/aarch64-cores.def @@ -46,6 +46,7 @@ /* ARMv8-A Architecture Processors. */ /* ARM ('A') cores. */ +AARCH64_CORE("cortex-a34", cortexa34, cortexa53, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa35, 0x41, 0xd02, -1) AARCH64_CORE("cortex-a35", cortexa35, cortexa53, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa35, 0x41, 0xd04, -1) AARCH64_CORE("cortex-a53", cortexa53, cortexa53, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa53, 0x41, 0xd03, -1) AARCH64_CORE("cortex-a57", cortexa57, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa57, 0x41, 0xd07, -1) @@ -100,6 +101,10 @@ AARCH64_CORE("thunderx2t99", thunderx2t99, thunderx2t99, 8_1A, AARCH64_FL_FOR AARCH64_CORE("cortex-a55", cortexa55, cortexa53, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD, cortexa53, 0x41, 0xd05, -1) AARCH64_CORE("cortex-a75", cortexa75, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD, cortexa73, 0x41, 0xd0a, -1) AARCH64_CORE("cortex-a76", cortexa76, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD, cortexa72, 0x41, 0xd0b, -1) +AARCH64_CORE("cortex-a76ae", cortexa76ae, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD | AARCH64_FL_SSBS, cortexa72, 0x41, 0xd0e, -1) +AARCH64_CORE("cortex-a77", cortexa77, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD | AARCH64_FL_SSBS, cortexa72, 0x41, 0xd0d, -1) +AARCH64_CORE("cortex-a65", cortexa65, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD | AARCH64_FL_SSBS, cortexa73, 0x41, 0xd06, -1) +AARCH64_CORE("cortex-a65ae", cortexa65ae, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD | AARCH64_FL_SSBS, cortexa73, 0x41, 0xd43, -1) AARCH64_CORE("ares", ares, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD | AARCH64_FL_PROFILE, neoversen1, 0x41, 0xd0c, -1) AARCH64_CORE("neoverse-n1", neoversen1, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD | AARCH64_FL_PROFILE, neoversen1, 0x41, 0xd0c, -1) AARCH64_CORE("neoverse-e1", neoversee1, cortexa53, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD | AARCH64_FL_SSBS, cortexa53, 0x41, 0xd4a, -1) diff --git a/gcc/config/aarch64/aarch64-tune.md b/gcc/config/aarch64/aarch64-tune.md index 2b1ec85ae31..a6a14b7fc77 100644 --- a/gcc/config/aarch64/aarch64-tune.md +++ b/gcc/config/aarch64/aarch64-tune.md @@ -1,5 +1,5 @@ ;; -*- buffer-read-only: t -*- ;; Generated automatically by gentune.sh from aarch64-cores.def (define_attr "tune" - "cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,octeontx,octeontxt81,octeontxt83,thunderxt81,thunderxt83,emag,xgene1,falkor,qdf24xx,exynosm1,phecda,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,ares,neoversen1,neoversee1,tsv110,saphira,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55,cortexa76cortexa55" + "cortexa34,cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,octeontx,octeontxt81,octeontxt83,thunderxt81,thunderxt83,emag,xgene1,falkor,qdf24xx,exynosm1,phecda,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,cortexa76ae,cortexa77,cortexa65,cortexa65ae,ares,neoversen1,neoversee1,tsv110,saphira,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55,cortexa76cortexa55" (const (symbol_ref "((enum attr_tune) aarch64_tune)"))) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 29585cf15aa..3aa59b9a125 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -15809,7 +15809,9 @@ Specify the name of the target processor for which GCC should tune the performance of the code. Permissible values for this option are: @samp{generic}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a55}, @samp{cortex-a57}, @samp{cortex-a72}, @samp{cortex-a73}, @samp{cortex-a75}, -@samp{cortex-a76}, @samp{ares}, @samp{exynos-m1}, @samp{emag}, @samp{falkor}, +@samp{cortex-a76}, @samp{cortex-a76ae}, @samp{cortex-a77}, +@samp{cortex-a65}, @samp{cortex-a65ae}, @samp{cortex-a34}, +@samp{ares}, @samp{exynos-m1}, @samp{emag}, @samp{falkor}, @samp{neoverse-e1},@samp{neoverse-n1},@samp{qdf24xx}, @samp{saphira}, @samp{phecda}, @samp{xgene1}, @samp{vulcan}, @samp{octeontx}, @samp{octeontx81}, @samp{octeontx83}, @samp{thunderx}, @samp{thunderxt88},