| Message ID | 20190705151440.20844-2-manivannan.sadhasivam@linaro.org |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | Add Bitmain BM1880 clock driver | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | warning | "total: 1 errors, 2 warnings, 129 lines checked" |
On Fri, Jul 05, 2019 at 08:44:36PM +0530, Manivannan Sadhasivam wrote: > Add devicetree binding for Bitmain BM1880 SoC clock controller. > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- > .../bindings/clock/bitmain,bm1880-clk.txt | 47 +++++++++++ > include/dt-bindings/clock/bm1880-clock.h | 82 +++++++++++++++++++ > 2 files changed, 129 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.txt > create mode 100644 include/dt-bindings/clock/bm1880-clock.h > > diff --git a/Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.txt b/Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.txt > new file mode 100644 > index 000000000000..9c967095d430 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.txt > @@ -0,0 +1,47 @@ > +* Bitmain BM1880 Clock Controller > + > +The Bitmain BM1880 clock controler generates and supplies clock to checkpatch.pl reports a spelling error... > +various peripherals within the SoC. > + > +Required Properties: > + > +- compatible: Should be "bitmain,bm1880-clk" > +- reg : Register address and size of PLL and SYS control domains > +- reg-names : Register domain names: "pll" and "sys" > +- clocks : Phandle of the input reference clock. > +- #clock-cells: Should be 1. > + > +Each clock is assigned an identifier, and client nodes can use this identifier > +to specify the clock which they consume. > + > +All available clocks are defined as preprocessor macros in corresponding > +dt-bindings/clock/bm1880-clock.h header and can be used in device tree sources. > + > +External clocks: > + > +The osc clock used as the input for the plls is generated outside the SoC. > +It is expected that it is defined using standard clock bindings as "osc". > + > +Example: > + > + clk: clock-controller@800 { Usually the unit-address is from the first entry. > + compatible = "bitmain,bm1880-clk"; > + reg = <0xe8 0x0c>,<0x800 0xb0>; space ^ > + reg-names = "pll", "sys"; > + clocks = <&osc>; > + #clock-cells = <1>; > + }; > + > +Example: UART controller node that consumes clock generated by the clock > +controller: > + > + uart0: serial@58018000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x0 0x58018000 0x0 0x2000>; > + clocks = <&clk BM1880_CLK_UART_500M>; > + <&clk BM1880_CLK_APB_UART>; > + clock-names = "baudclk", "apb_pclk"; > + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; > + reg-shift = <2>; > + reg-io-width = <4>; > + }; > diff --git a/include/dt-bindings/clock/bm1880-clock.h b/include/dt-bindings/clock/bm1880-clock.h > new file mode 100644 > index 000000000000..764472b9a4fd > --- /dev/null > +++ b/include/dt-bindings/clock/bm1880-clock.h > @@ -0,0 +1,82 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Device Tree binding constants for Bitmain BM1880 SoC > + * > + * Copyright (c) 2019 Linaro Ltd. > + */ > + > +#ifndef __DT_BINDINGS_CLOCK_BM1880_H > +#define __DT_BINDINGS_CLOCK_BM1880_H > + > +#define BM1880_CLK_OSC 0 > +#define BM1880_CLK_MPLL 1 > +#define BM1880_CLK_SPLL 2 > +#define BM1880_CLK_FPLL 3 > +#define BM1880_CLK_DDRPLL 4 space before tab > +#define BM1880_CLK_A53 5 > +#define BM1880_CLK_50M_A53 6 > +#define BM1880_CLK_AHB_ROM 7 > +#define BM1880_CLK_AXI_SRAM 8 > +#define BM1880_CLK_DDR_AXI 9 > +#define BM1880_CLK_EFUSE 10 > +#define BM1880_CLK_APB_EFUSE 11 > +#define BM1880_CLK_AXI5_EMMC 12 > +#define BM1880_CLK_EMMC 13 > +#define BM1880_CLK_100K_EMMC 14 > +#define BM1880_CLK_AXI5_SD 15 > +#define BM1880_CLK_SD 16 > +#define BM1880_CLK_100K_SD 17 > +#define BM1880_CLK_500M_ETH0 18 > +#define BM1880_CLK_AXI4_ETH0 19 > +#define BM1880_CLK_500M_ETH1 20 > +#define BM1880_CLK_AXI4_ETH1 21 > +#define BM1880_CLK_AXI1_GDMA 22 > +#define BM1880_CLK_APB_GPIO 23 > +#define BM1880_CLK_APB_GPIO_INTR 24 > +#define BM1880_CLK_GPIO_DB 25 > +#define BM1880_CLK_AXI1_MINER 26 > +#define BM1880_CLK_AHB_SF 27 > +#define BM1880_CLK_SDMA_AXI 28 > +#define BM1880_CLK_SDMA_AUD 29 > +#define BM1880_CLK_APB_I2C 30 > +#define BM1880_CLK_APB_WDT 31 > +#define BM1880_CLK_APB_JPEG 32 > +#define BM1880_CLK_JPEG_AXI 33 > +#define BM1880_CLK_AXI5_NF 34 > +#define BM1880_CLK_APB_NF 35 > +#define BM1880_CLK_NF 36 > +#define BM1880_CLK_APB_PWM 37 > +#define BM1880_CLK_DIV_0_RV 38 > +#define BM1880_CLK_DIV_1_RV 39 > +#define BM1880_CLK_MUX_RV 40 > +#define BM1880_CLK_RV 41 > +#define BM1880_CLK_APB_SPI 42 > +#define BM1880_CLK_TPU_AXI 43 > +#define BM1880_CLK_DIV_UART_500M 44 > +#define BM1880_CLK_UART_500M 45 > +#define BM1880_CLK_APB_UART 46 > +#define BM1880_CLK_APB_I2S 47 > +#define BM1880_CLK_AXI4_USB 48 > +#define BM1880_CLK_APB_USB 49 > +#define BM1880_CLK_125M_USB 50 > +#define BM1880_CLK_33K_USB 51 > +#define BM1880_CLK_DIV_12M_USB 52 > +#define BM1880_CLK_12M_USB 53 > +#define BM1880_CLK_APB_VIDEO 54 > +#define BM1880_CLK_VIDEO_AXI 55 > +#define BM1880_CLK_VPP_AXI 56 > +#define BM1880_CLK_APB_VPP 57 > +#define BM1880_CLK_DIV_0_AXI1 58 > +#define BM1880_CLK_DIV_1_AXI1 59 > +#define BM1880_CLK_AXI1 60 > +#define BM1880_CLK_AXI2 61 > +#define BM1880_CLK_AXI3 62 > +#define BM1880_CLK_AXI4 63 > +#define BM1880_CLK_AXI5 64 > +#define BM1880_CLK_DIV_0_AXI6 65 > +#define BM1880_CLK_DIV_1_AXI6 66 > +#define BM1880_CLK_MUX_AXI6 67 > +#define BM1880_CLK_AXI6 68 > +#define BM1880_NR_CLKS 69 > + > +#endif /* __DT_BINDINGS_CLOCK_BM1880_H */ > -- > 2.17.1 >
Quoting Manivannan Sadhasivam (2019-07-05 08:14:36) > Add devicetree binding for Bitmain BM1880 SoC clock controller. > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- > .../bindings/clock/bitmain,bm1880-clk.txt | 47 +++++++++++ Can you convert this to YAML? It's all the rage right now. > include/dt-bindings/clock/bm1880-clock.h | 82 +++++++++++++++++++ > 2 files changed, 129 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.txt > create mode 100644 include/dt-bindings/clock/bm1880-clock.h > > diff --git a/Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.txt b/Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.txt > new file mode 100644 > index 000000000000..9c967095d430 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.txt > @@ -0,0 +1,47 @@ > +* Bitmain BM1880 Clock Controller > + > +The Bitmain BM1880 clock controler generates and supplies clock to > +various peripherals within the SoC. > + > +Required Properties: > + > +- compatible: Should be "bitmain,bm1880-clk" > +- reg : Register address and size of PLL and SYS control domains > +- reg-names : Register domain names: "pll" and "sys" > +- clocks : Phandle of the input reference clock. > +- #clock-cells: Should be 1. > + > +Each clock is assigned an identifier, and client nodes can use this identifier > +to specify the clock which they consume. > + > +All available clocks are defined as preprocessor macros in corresponding > +dt-bindings/clock/bm1880-clock.h header and can be used in device tree sources. > + > +External clocks: > + > +The osc clock used as the input for the plls is generated outside the SoC. > +It is expected that it is defined using standard clock bindings as "osc". > + > +Example: > + > + clk: clock-controller@800 { > + compatible = "bitmain,bm1880-clk"; > + reg = <0xe8 0x0c>,<0x800 0xb0>; It looks weird still. What hardware module is this actually part of? Some larger power manager block? > + reg-names = "pll", "sys"; > + clocks = <&osc>; > + #clock-cells = <1>; > + }; > +
Hi Stephen, On Wed, Aug 07, 2019 at 10:01:28PM -0700, Stephen Boyd wrote: > Quoting Manivannan Sadhasivam (2019-07-05 08:14:36) > > Add devicetree binding for Bitmain BM1880 SoC clock controller. > > > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > > --- > > .../bindings/clock/bitmain,bm1880-clk.txt | 47 +++++++++++ > > Can you convert this to YAML? It's all the rage right now. > Sure. > > include/dt-bindings/clock/bm1880-clock.h | 82 +++++++++++++++++++ > > 2 files changed, 129 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.txt > > create mode 100644 include/dt-bindings/clock/bm1880-clock.h > > > > diff --git a/Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.txt b/Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.txt > > new file mode 100644 > > index 000000000000..9c967095d430 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.txt > > @@ -0,0 +1,47 @@ > > +* Bitmain BM1880 Clock Controller > > + > > +The Bitmain BM1880 clock controler generates and supplies clock to > > +various peripherals within the SoC. > > + > > +Required Properties: > > + > > +- compatible: Should be "bitmain,bm1880-clk" > > +- reg : Register address and size of PLL and SYS control domains > > +- reg-names : Register domain names: "pll" and "sys" > > +- clocks : Phandle of the input reference clock. > > +- #clock-cells: Should be 1. > > + > > +Each clock is assigned an identifier, and client nodes can use this identifier > > +to specify the clock which they consume. > > + > > +All available clocks are defined as preprocessor macros in corresponding > > +dt-bindings/clock/bm1880-clock.h header and can be used in device tree sources. > > + > > +External clocks: > > + > > +The osc clock used as the input for the plls is generated outside the SoC. > > +It is expected that it is defined using standard clock bindings as "osc". > > + > > +Example: > > + > > + clk: clock-controller@800 { > > + compatible = "bitmain,bm1880-clk"; > > + reg = <0xe8 0x0c>,<0x800 0xb0>; > > It looks weird still. What hardware module is this actually part of? > Some larger power manager block? > These are all part of the sysctrl block (clock + pinctrl + reset) and the register domains got split between system and pll. Thanks, Mani > > + reg-names = "pll", "sys"; > > + clocks = <&osc>; > > + #clock-cells = <1>; > > + }; > > +
Quoting Manivannan Sadhasivam (2019-08-16 20:34:22) > On Wed, Aug 07, 2019 at 10:01:28PM -0700, Stephen Boyd wrote: > > Quoting Manivannan Sadhasivam (2019-07-05 08:14:36) > > > +It is expected that it is defined using standard clock bindings as "osc". > > > + > > > +Example: > > > + > > > + clk: clock-controller@800 { > > > + compatible = "bitmain,bm1880-clk"; > > > + reg = <0xe8 0x0c>,<0x800 0xb0>; > > > > It looks weird still. What hardware module is this actually part of? > > Some larger power manager block? > > > > These are all part of the sysctrl block (clock + pinctrl + reset) and the > register domains got split between system and pll. > And that can't be one node that probes the clk, pinctrl, and reset drivers from C code?
On Fri, Aug 16, 2019 at 08:46:11PM -0700, Stephen Boyd wrote: > Quoting Manivannan Sadhasivam (2019-08-16 20:34:22) > > On Wed, Aug 07, 2019 at 10:01:28PM -0700, Stephen Boyd wrote: > > > Quoting Manivannan Sadhasivam (2019-07-05 08:14:36) > > > > +It is expected that it is defined using standard clock bindings as "osc". > > > > + > > > > +Example: > > > > + > > > > + clk: clock-controller@800 { > > > > + compatible = "bitmain,bm1880-clk"; > > > > + reg = <0xe8 0x0c>,<0x800 0xb0>; > > > > > > It looks weird still. What hardware module is this actually part of? > > > Some larger power manager block? > > > > > > > These are all part of the sysctrl block (clock + pinctrl + reset) and the > > register domains got split between system and pll. > > > > And that can't be one node that probes the clk, pinctrl, and reset > drivers from C code? It is not a MFD for sure. It's just grouping of the register domains together. Thanks, Mani >
Quoting Manivannan Sadhasivam (2019-08-16 20:58:45) > On Fri, Aug 16, 2019 at 08:46:11PM -0700, Stephen Boyd wrote: > > Quoting Manivannan Sadhasivam (2019-08-16 20:34:22) > > > On Wed, Aug 07, 2019 at 10:01:28PM -0700, Stephen Boyd wrote: > > > > Quoting Manivannan Sadhasivam (2019-07-05 08:14:36) > > > > > +It is expected that it is defined using standard clock bindings as "osc". > > > > > + > > > > > +Example: > > > > > + > > > > > + clk: clock-controller@800 { > > > > > + compatible = "bitmain,bm1880-clk"; > > > > > + reg = <0xe8 0x0c>,<0x800 0xb0>; > > > > > > > > It looks weird still. What hardware module is this actually part of? > > > > Some larger power manager block? > > > > > > > > > > These are all part of the sysctrl block (clock + pinctrl + reset) and the > > > register domains got split between system and pll. > > > > > > > And that can't be one node that probes the clk, pinctrl, and reset > > drivers from C code? > > It is not a MFD for sure. It's just grouping of the register domains together. > Are there datasheets? I'm not saying it's an "MFD", just saying that it's one hardware IP block delivered by the SoC integrator. It's already odd that there are two register properties.
diff --git a/Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.txt b/Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.txt new file mode 100644 index 000000000000..9c967095d430 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.txt @@ -0,0 +1,47 @@ +* Bitmain BM1880 Clock Controller + +The Bitmain BM1880 clock controler generates and supplies clock to +various peripherals within the SoC. + +Required Properties: + +- compatible: Should be "bitmain,bm1880-clk" +- reg : Register address and size of PLL and SYS control domains +- reg-names : Register domain names: "pll" and "sys" +- clocks : Phandle of the input reference clock. +- #clock-cells: Should be 1. + +Each clock is assigned an identifier, and client nodes can use this identifier +to specify the clock which they consume. + +All available clocks are defined as preprocessor macros in corresponding +dt-bindings/clock/bm1880-clock.h header and can be used in device tree sources. + +External clocks: + +The osc clock used as the input for the plls is generated outside the SoC. +It is expected that it is defined using standard clock bindings as "osc". + +Example: + + clk: clock-controller@800 { + compatible = "bitmain,bm1880-clk"; + reg = <0xe8 0x0c>,<0x800 0xb0>; + reg-names = "pll", "sys"; + clocks = <&osc>; + #clock-cells = <1>; + }; + +Example: UART controller node that consumes clock generated by the clock +controller: + + uart0: serial@58018000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x58018000 0x0 0x2000>; + clocks = <&clk BM1880_CLK_UART_500M>; + <&clk BM1880_CLK_APB_UART>; + clock-names = "baudclk", "apb_pclk"; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + }; diff --git a/include/dt-bindings/clock/bm1880-clock.h b/include/dt-bindings/clock/bm1880-clock.h new file mode 100644 index 000000000000..764472b9a4fd --- /dev/null +++ b/include/dt-bindings/clock/bm1880-clock.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Device Tree binding constants for Bitmain BM1880 SoC + * + * Copyright (c) 2019 Linaro Ltd. + */ + +#ifndef __DT_BINDINGS_CLOCK_BM1880_H +#define __DT_BINDINGS_CLOCK_BM1880_H + +#define BM1880_CLK_OSC 0 +#define BM1880_CLK_MPLL 1 +#define BM1880_CLK_SPLL 2 +#define BM1880_CLK_FPLL 3 +#define BM1880_CLK_DDRPLL 4 +#define BM1880_CLK_A53 5 +#define BM1880_CLK_50M_A53 6 +#define BM1880_CLK_AHB_ROM 7 +#define BM1880_CLK_AXI_SRAM 8 +#define BM1880_CLK_DDR_AXI 9 +#define BM1880_CLK_EFUSE 10 +#define BM1880_CLK_APB_EFUSE 11 +#define BM1880_CLK_AXI5_EMMC 12 +#define BM1880_CLK_EMMC 13 +#define BM1880_CLK_100K_EMMC 14 +#define BM1880_CLK_AXI5_SD 15 +#define BM1880_CLK_SD 16 +#define BM1880_CLK_100K_SD 17 +#define BM1880_CLK_500M_ETH0 18 +#define BM1880_CLK_AXI4_ETH0 19 +#define BM1880_CLK_500M_ETH1 20 +#define BM1880_CLK_AXI4_ETH1 21 +#define BM1880_CLK_AXI1_GDMA 22 +#define BM1880_CLK_APB_GPIO 23 +#define BM1880_CLK_APB_GPIO_INTR 24 +#define BM1880_CLK_GPIO_DB 25 +#define BM1880_CLK_AXI1_MINER 26 +#define BM1880_CLK_AHB_SF 27 +#define BM1880_CLK_SDMA_AXI 28 +#define BM1880_CLK_SDMA_AUD 29 +#define BM1880_CLK_APB_I2C 30 +#define BM1880_CLK_APB_WDT 31 +#define BM1880_CLK_APB_JPEG 32 +#define BM1880_CLK_JPEG_AXI 33 +#define BM1880_CLK_AXI5_NF 34 +#define BM1880_CLK_APB_NF 35 +#define BM1880_CLK_NF 36 +#define BM1880_CLK_APB_PWM 37 +#define BM1880_CLK_DIV_0_RV 38 +#define BM1880_CLK_DIV_1_RV 39 +#define BM1880_CLK_MUX_RV 40 +#define BM1880_CLK_RV 41 +#define BM1880_CLK_APB_SPI 42 +#define BM1880_CLK_TPU_AXI 43 +#define BM1880_CLK_DIV_UART_500M 44 +#define BM1880_CLK_UART_500M 45 +#define BM1880_CLK_APB_UART 46 +#define BM1880_CLK_APB_I2S 47 +#define BM1880_CLK_AXI4_USB 48 +#define BM1880_CLK_APB_USB 49 +#define BM1880_CLK_125M_USB 50 +#define BM1880_CLK_33K_USB 51 +#define BM1880_CLK_DIV_12M_USB 52 +#define BM1880_CLK_12M_USB 53 +#define BM1880_CLK_APB_VIDEO 54 +#define BM1880_CLK_VIDEO_AXI 55 +#define BM1880_CLK_VPP_AXI 56 +#define BM1880_CLK_APB_VPP 57 +#define BM1880_CLK_DIV_0_AXI1 58 +#define BM1880_CLK_DIV_1_AXI1 59 +#define BM1880_CLK_AXI1 60 +#define BM1880_CLK_AXI2 61 +#define BM1880_CLK_AXI3 62 +#define BM1880_CLK_AXI4 63 +#define BM1880_CLK_AXI5 64 +#define BM1880_CLK_DIV_0_AXI6 65 +#define BM1880_CLK_DIV_1_AXI6 66 +#define BM1880_CLK_MUX_AXI6 67 +#define BM1880_CLK_AXI6 68 +#define BM1880_NR_CLKS 69 + +#endif /* __DT_BINDINGS_CLOCK_BM1880_H */
Add devicetree binding for Bitmain BM1880 SoC clock controller. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> --- .../bindings/clock/bitmain,bm1880-clk.txt | 47 +++++++++++ include/dt-bindings/clock/bm1880-clock.h | 82 +++++++++++++++++++ 2 files changed, 129 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.txt create mode 100644 include/dt-bindings/clock/bm1880-clock.h