| Message ID | 20190713034634.44585-8-icenowy@aosc.io |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | Support for Allwinner V3/S3L and Sochip S3 | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success |
On Fri, Jul 12, 2019 at 9:49 PM Icenowy Zheng <icenowy@aosc.io> wrote: > > The Lichee Zero Plus is a core board made by Sipeed, with a microUSB > connector on it, TF slot or WSON8 SD chip, optional eMMC or SPI Flash. > It has a gold finger connector for expansion, and UART is available from > reserved pins w/ 2.54mm pitch. The board can use either SoChip S3 or > Allwinner V3L SoCs. > > Add the device tree binding of the basic version of the core board -- > w/o eMMC or SPI Flash, w/ TF slot or WSON8 SD, and use S3 SoC. > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> > --- > No changes since v3. > > Patch introduced in v2. > > Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++ > 1 file changed, 5 insertions(+) Reviewed-by: Rob Herring <robh@kernel.org> Rob
On Sat, Jul 13, 2019 at 11:46:33AM +0800, Icenowy Zheng wrote: > The Lichee Zero Plus is a core board made by Sipeed, with a microUSB > connector on it, TF slot or WSON8 SD chip, optional eMMC or SPI Flash. > It has a gold finger connector for expansion, and UART is available from > reserved pins w/ 2.54mm pitch. The board can use either SoChip S3 or > Allwinner V3L SoCs. > > Add the device tree binding of the basic version of the core board -- > w/o eMMC or SPI Flash, w/ TF slot or WSON8 SD, and use S3 SoC. > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> > --- > No changes since v3. > > Patch introduced in v2. > > Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml > index 000a00d12d6a..48c126a7a848 100644 > --- a/Documentation/devicetree/bindings/arm/sunxi.yaml > +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml > @@ -353,6 +353,11 @@ properties: > - const: licheepi,licheepi-zero > - const: allwinner,sun8i-v3s > > + - description: Lichee Zero Plus (with S3, without eMMC/SPI Flash) > + items: > + - const: sipeed,lichee-zero-plus > + - const: allwinner,sun8i-s3 If the S3 is just a rebranded V3, then we should have the v3 compatile in that list too. Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com
于 2019年7月20日 GMT+08:00 下午6:13:18, Maxime Ripard <maxime.ripard@bootlin.com> 写到: >On Sat, Jul 13, 2019 at 11:46:33AM +0800, Icenowy Zheng wrote: >> The Lichee Zero Plus is a core board made by Sipeed, with a microUSB >> connector on it, TF slot or WSON8 SD chip, optional eMMC or SPI >Flash. >> It has a gold finger connector for expansion, and UART is available >from >> reserved pins w/ 2.54mm pitch. The board can use either SoChip S3 or >> Allwinner V3L SoCs. >> >> Add the device tree binding of the basic version of the core board -- >> w/o eMMC or SPI Flash, w/ TF slot or WSON8 SD, and use S3 SoC. >> >> Signed-off-by: Icenowy Zheng <icenowy@aosc.io> >> --- >> No changes since v3. >> >> Patch introduced in v2. >> >> Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++ >> 1 file changed, 5 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml >b/Documentation/devicetree/bindings/arm/sunxi.yaml >> index 000a00d12d6a..48c126a7a848 100644 >> --- a/Documentation/devicetree/bindings/arm/sunxi.yaml >> +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml >> @@ -353,6 +353,11 @@ properties: >> - const: licheepi,licheepi-zero >> - const: allwinner,sun8i-v3s >> >> + - description: Lichee Zero Plus (with S3, without eMMC/SPI >Flash) >> + items: >> + - const: sipeed,lichee-zero-plus >> + - const: allwinner,sun8i-s3 > >If the S3 is just a rebranded V3, then we should have the v3 compatile >in that list too. S3 is V3 with copackaged DDR3 DRAM. It's pin incompatible w/ V3. > >Maxime > >-- >Maxime Ripard, Bootlin >Embedded Linux and Kernel engineering >https://bootlin.com
On Sat, Jul 20, 2019 at 07:39:08PM +0800, Icenowy Zheng wrote: > > > 于 2019年7月20日 GMT+08:00 下午6:13:18, Maxime Ripard <maxime.ripard@bootlin.com> 写到: > >On Sat, Jul 13, 2019 at 11:46:33AM +0800, Icenowy Zheng wrote: > >> The Lichee Zero Plus is a core board made by Sipeed, with a microUSB > >> connector on it, TF slot or WSON8 SD chip, optional eMMC or SPI > >Flash. > >> It has a gold finger connector for expansion, and UART is available > >from > >> reserved pins w/ 2.54mm pitch. The board can use either SoChip S3 or > >> Allwinner V3L SoCs. > >> > >> Add the device tree binding of the basic version of the core board -- > >> w/o eMMC or SPI Flash, w/ TF slot or WSON8 SD, and use S3 SoC. > >> > >> Signed-off-by: Icenowy Zheng <icenowy@aosc.io> > >> --- > >> No changes since v3. > >> > >> Patch introduced in v2. > >> > >> Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++ > >> 1 file changed, 5 insertions(+) > >> > >> diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml > >b/Documentation/devicetree/bindings/arm/sunxi.yaml > >> index 000a00d12d6a..48c126a7a848 100644 > >> --- a/Documentation/devicetree/bindings/arm/sunxi.yaml > >> +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml > >> @@ -353,6 +353,11 @@ properties: > >> - const: licheepi,licheepi-zero > >> - const: allwinner,sun8i-v3s > >> > >> + - description: Lichee Zero Plus (with S3, without eMMC/SPI > >Flash) > >> + items: > >> + - const: sipeed,lichee-zero-plus > >> + - const: allwinner,sun8i-s3 > > > >If the S3 is just a rebranded V3, then we should have the v3 compatile > >in that list too. > > S3 is V3 with copackaged DDR3 DRAM. > > It's pin incompatible w/ V3. Does it matter though? If the only thing that changes is the package, we're not manipulating that, and any software that deals with the v3 can deal with the s3. Which is what the compatible is about. Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com
在 2019-07-23 03:29，Maxime Ripard 写道： > On Sat, Jul 20, 2019 at 07:39:08PM +0800, Icenowy Zheng wrote: >> >> >> 于 2019年7月20日 GMT+08:00 下午6:13:18, Maxime Ripard >> <maxime.ripard@bootlin.com> 写到: >> >On Sat, Jul 13, 2019 at 11:46:33AM +0800, Icenowy Zheng wrote: >> >> The Lichee Zero Plus is a core board made by Sipeed, with a microUSB >> >> connector on it, TF slot or WSON8 SD chip, optional eMMC or SPI >> >Flash. >> >> It has a gold finger connector for expansion, and UART is available >> >from >> >> reserved pins w/ 2.54mm pitch. The board can use either SoChip S3 or >> >> Allwinner V3L SoCs. >> >> >> >> Add the device tree binding of the basic version of the core board -- >> >> w/o eMMC or SPI Flash, w/ TF slot or WSON8 SD, and use S3 SoC. >> >> >> >> Signed-off-by: Icenowy Zheng <icenowy@aosc.io> >> >> --- >> >> No changes since v3. >> >> >> >> Patch introduced in v2. >> >> >> >> Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++ >> >> 1 file changed, 5 insertions(+) >> >> >> >> diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml >> >b/Documentation/devicetree/bindings/arm/sunxi.yaml >> >> index 000a00d12d6a..48c126a7a848 100644 >> >> --- a/Documentation/devicetree/bindings/arm/sunxi.yaml >> >> +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml >> >> @@ -353,6 +353,11 @@ properties: >> >> - const: licheepi,licheepi-zero >> >> - const: allwinner,sun8i-v3s >> >> >> >> + - description: Lichee Zero Plus (with S3, without eMMC/SPI >> >Flash) >> >> + items: >> >> + - const: sipeed,lichee-zero-plus >> >> + - const: allwinner,sun8i-s3 >> > >> >If the S3 is just a rebranded V3, then we should have the v3 compatile >> >in that list too. >> >> S3 is V3 with copackaged DDR3 DRAM. >> >> It's pin incompatible w/ V3. > > Does it matter though? > > If the only thing that changes is the package, we're not manipulating > that, and any software that deals with the v3 can deal with the > s3. Which is what the compatible is about. Okay. Should the S3 compatible be kept befoer the V3 one? > > Maxime > > -- > Maxime Ripard, Bootlin > Embedded Linux and Kernel engineering > https://bootlin.com > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
On Wed, Jul 24, 2019 at 09:09:01PM +0800, Icenowy Zheng wrote: > 在 2019-07-23 03:29，Maxime Ripard 写道： > > On Sat, Jul 20, 2019 at 07:39:08PM +0800, Icenowy Zheng wrote: > > > > > > > > > 于 2019年7月20日 GMT+08:00 下午6:13:18, Maxime Ripard > > > <maxime.ripard@bootlin.com> 写到: > > > >On Sat, Jul 13, 2019 at 11:46:33AM +0800, Icenowy Zheng wrote: > > > >> The Lichee Zero Plus is a core board made by Sipeed, with a microUSB > > > >> connector on it, TF slot or WSON8 SD chip, optional eMMC or SPI > > > >Flash. > > > >> It has a gold finger connector for expansion, and UART is available > > > >from > > > >> reserved pins w/ 2.54mm pitch. The board can use either SoChip S3 or > > > >> Allwinner V3L SoCs. > > > >> > > > >> Add the device tree binding of the basic version of the core board -- > > > >> w/o eMMC or SPI Flash, w/ TF slot or WSON8 SD, and use S3 SoC. > > > >> > > > >> Signed-off-by: Icenowy Zheng <icenowy@aosc.io> > > > >> --- > > > >> No changes since v3. > > > >> > > > >> Patch introduced in v2. > > > >> > > > >> Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++ > > > >> 1 file changed, 5 insertions(+) > > > >> > > > >> diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml > > > >b/Documentation/devicetree/bindings/arm/sunxi.yaml > > > >> index 000a00d12d6a..48c126a7a848 100644 > > > >> --- a/Documentation/devicetree/bindings/arm/sunxi.yaml > > > >> +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml > > > >> @@ -353,6 +353,11 @@ properties: > > > >> - const: licheepi,licheepi-zero > > > >> - const: allwinner,sun8i-v3s > > > >> > > > >> + - description: Lichee Zero Plus (with S3, without eMMC/SPI > > > >Flash) > > > >> + items: > > > >> + - const: sipeed,lichee-zero-plus > > > >> + - const: allwinner,sun8i-s3 > > > > > > > >If the S3 is just a rebranded V3, then we should have the v3 compatile > > > >in that list too. > > > > > > S3 is V3 with copackaged DDR3 DRAM. > > > > > > It's pin incompatible w/ V3. > > > > Does it matter though? > > > > If the only thing that changes is the package, we're not manipulating > > that, and any software that deals with the v3 can deal with the > > s3. Which is what the compatible is about. > > Okay. Should the S3 compatible be kept befoer the V3 one? Yep, something like (in the DT) compatible = "sipeed,lichee-zero-plus", "allwinner,sun8i-s3", "allwinner,sun8i-v3" Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com
diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index 000a00d12d6a..48c126a7a848 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -353,6 +353,11 @@ properties: - const: licheepi,licheepi-zero - const: allwinner,sun8i-v3s + - description: Lichee Zero Plus (with S3, without eMMC/SPI Flash) + items: + - const: sipeed,lichee-zero-plus + - const: allwinner,sun8i-s3 + - description: Linksprite PCDuino items: - const: linksprite,a10-pcduino
The Lichee Zero Plus is a core board made by Sipeed, with a microUSB connector on it, TF slot or WSON8 SD chip, optional eMMC or SPI Flash. It has a gold finger connector for expansion, and UART is available from reserved pins w/ 2.54mm pitch. The board can use either SoChip S3 or Allwinner V3L SoCs. Add the device tree binding of the basic version of the core board -- w/o eMMC or SPI Flash, w/ TF slot or WSON8 SD, and use S3 SoC. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> --- No changes since v3. Patch introduced in v2. Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++ 1 file changed, 5 insertions(+)