Message ID | 20190711174635.770-7-alex.hung@canonical.com |
---|---|
State | Superseded |
Headers | show |
Series | Updates architectural MSRs in IA32_MSRs | expand |
On 7/12/19 1:46 AM, Alex Hung wrote: > BIT definition is as below: > > 0 High-Temperature Interrupt Enable > 1 Low-Temperature Interrupt Enable > 2 PROCHOT# Interrupt Enable > 3 FORCEPR# Interrupt Enable > 4 Critical Temperature Interrupt Enable > 7:5 Reserved > 14:8 Threshold #1 Value > 15 Threshold #1 Interrupt Enable > 22:16 Threshold #2 Value > 23 Threshold #2 Interrupt Enable > 24 Power Limit Notification Enable > 63:25 Reserved > > Signed-off-by: Alex Hung <alex.hung@canonical.com> > --- > src/cpu/msr/msr.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/src/cpu/msr/msr.c b/src/cpu/msr/msr.c > index 6e28bc1c..3ff32c95 100644 > --- a/src/cpu/msr/msr.c > +++ b/src/cpu/msr/msr.c > @@ -361,7 +361,7 @@ static const msr_info IA32_MSRs[] = { > { "MCG_STATUS", 0x0000017a, 0xffffffffffffffffULL, NULL }, > { "MCG_CTL", 0x0000017b, 0xffffffffffffffffULL, NULL }, > { "CLOCK_MODULATION", 0x0000019a, 0x000000000000001fULL, NULL }, > - { "THERM_INTERRUPT", 0x0000019b, 0x000000000180801fULL, NULL }, > + { "THERM_INTERRUPT", 0x0000019b, 0x000000001ffff1ffULL, NULL }, Should be { "THERM_INTERRUPT", 0x0000019b, 0x0000000001ffff1fULL, NULL }, ? Ivan > //{ "THERM_STATUS", 0x0000019c, 0x0000000080000fffULL, NULL }, > { "MISC_ENABLE", 0x000001a0, 0x0000000400c51889ULL, NULL }, > { "PACKAGE_THERM_INTERRUPT", 0x000001b2, 0x0000000001ffff17ULL, NULL }, >
On Wed, Jul 24, 2019 at 1:02 AM ivanhu <ivan.hu@canonical.com> wrote: > > > > On 7/12/19 1:46 AM, Alex Hung wrote: > > BIT definition is as below: > > > > 0 High-Temperature Interrupt Enable > > 1 Low-Temperature Interrupt Enable > > 2 PROCHOT# Interrupt Enable > > 3 FORCEPR# Interrupt Enable > > 4 Critical Temperature Interrupt Enable > > 7:5 Reserved > > 14:8 Threshold #1 Value > > 15 Threshold #1 Interrupt Enable > > 22:16 Threshold #2 Value > > 23 Threshold #2 Interrupt Enable > > 24 Power Limit Notification Enable > > 63:25 Reserved > > > > Signed-off-by: Alex Hung <alex.hung@canonical.com> > > --- > > src/cpu/msr/msr.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/src/cpu/msr/msr.c b/src/cpu/msr/msr.c > > index 6e28bc1c..3ff32c95 100644 > > --- a/src/cpu/msr/msr.c > > +++ b/src/cpu/msr/msr.c > > @@ -361,7 +361,7 @@ static const msr_info IA32_MSRs[] = { > > { "MCG_STATUS", 0x0000017a, 0xffffffffffffffffULL, NULL }, > > { "MCG_CTL", 0x0000017b, 0xffffffffffffffffULL, NULL }, > > { "CLOCK_MODULATION", 0x0000019a, 0x000000000000001fULL, NULL }, > > - { "THERM_INTERRUPT", 0x0000019b, 0x000000000180801fULL, NULL }, > > + { "THERM_INTERRUPT", 0x0000019b, 0x000000001ffff1ffULL, NULL }, > Should be > { "THERM_INTERRUPT", 0x0000019b, 0x0000000001ffff1fULL, NULL }, ? Thanks for catching this. V2 is sent for reviews. > > Ivan > > > //{ "THERM_STATUS", 0x0000019c, 0x0000000080000fffULL, NULL }, > > { "MISC_ENABLE", 0x000001a0, 0x0000000400c51889ULL, NULL }, > > { "PACKAGE_THERM_INTERRUPT", 0x000001b2, 0x0000000001ffff17ULL, NULL }, > > > > -- > fwts-devel mailing list > fwts-devel@lists.ubuntu.com > Modify settings or unsubscribe at: https://lists.ubuntu.com/mailman/listinfo/fwts-devel
diff --git a/src/cpu/msr/msr.c b/src/cpu/msr/msr.c index 6e28bc1c..3ff32c95 100644 --- a/src/cpu/msr/msr.c +++ b/src/cpu/msr/msr.c @@ -361,7 +361,7 @@ static const msr_info IA32_MSRs[] = { { "MCG_STATUS", 0x0000017a, 0xffffffffffffffffULL, NULL }, { "MCG_CTL", 0x0000017b, 0xffffffffffffffffULL, NULL }, { "CLOCK_MODULATION", 0x0000019a, 0x000000000000001fULL, NULL }, - { "THERM_INTERRUPT", 0x0000019b, 0x000000000180801fULL, NULL }, + { "THERM_INTERRUPT", 0x0000019b, 0x000000001ffff1ffULL, NULL }, //{ "THERM_STATUS", 0x0000019c, 0x0000000080000fffULL, NULL }, { "MISC_ENABLE", 0x000001a0, 0x0000000400c51889ULL, NULL }, { "PACKAGE_THERM_INTERRUPT", 0x000001b2, 0x0000000001ffff17ULL, NULL },
BIT definition is as below: 0 High-Temperature Interrupt Enable 1 Low-Temperature Interrupt Enable 2 PROCHOT# Interrupt Enable 3 FORCEPR# Interrupt Enable 4 Critical Temperature Interrupt Enable 7:5 Reserved 14:8 Threshold #1 Value 15 Threshold #1 Interrupt Enable 22:16 Threshold #2 Value 23 Threshold #2 Interrupt Enable 24 Power Limit Notification Enable 63:25 Reserved Signed-off-by: Alex Hung <alex.hung@canonical.com> --- src/cpu/msr/msr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)