| Message ID | CAKKbWA5AuDRDuczTd+tonhc7hi3L=nKX5MCjbspOvAPNR9odyg@mail.gmail.com |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | [v3] clocksource/drivers/npcm: fix GENMASK and timer operation | expand |
On Mon, 15 Jul 2019, Avi Fishman wrote: > clocksource/drivers/npcm: fix GENMASK and timer operation Don't repeat the subject line please > NPCM7XX_Tx_OPER GENMASK() changed from (27, 3) to (28, 27) Please do not write down WHAT the patch does. That can be seen from the patch itself. Tell why this is wrong and what's the potential problem. > Since NPCM7XX_REG_TICR0 register reset value of those bits was 0, > it did not cause an issue > > in npcm7xx_timer_oneshot() the original NPCM7XX_REG_TCSR0 register was > read again after masking it with ~NPCM7XX_Tx_OPER so the masking didn't > take effect. > > npcm7xx_timer_periodic() was not wrong but it wrote to NPCM7XX_REG_TICR0 > in a middle of read modify write to NPCM7XX_REG_TCSR0 which is > confusing. > > Signed-off-by: Avi Fishman <avifishman70@gmail.com> > --- > drivers/clocksource/timer-npcm7xx.c | 9 +++------ > 1 file changed, 3 insertions(+), 6 deletions(-) > > diff --git a/drivers/clocksource/timer-npcm7xx.c > b/drivers/clocksource/timer-npcm7xx.c > index 8a30da7f083b..9780ffd8010e 100644 > --- a/drivers/clocksource/timer-npcm7xx.c > +++ b/drivers/clocksource/timer-npcm7xx.c > @@ -32,7 +32,7 @@ > #define NPCM7XX_Tx_INTEN BIT(29) > #define NPCM7XX_Tx_COUNTEN BIT(30) > #define NPCM7XX_Tx_ONESHOT 0x0 > -#define NPCM7XX_Tx_OPER GENMASK(27, 3) > +#define NPCM7XX_Tx_OPER GENMASK(28, 27) > #define NPCM7XX_Tx_MIN_PRESCALE 0x1 > #define NPCM7XX_Tx_TDR_MASK_BITS 24 > #define NPCM7XX_Tx_MAX_CNT 0xFFFFFF > @@ -84,8 +84,6 @@ static int npcm7xx_timer_oneshot(struct > clock_event_device *evt) > > val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0); > val &= ~NPCM7XX_Tx_OPER; > - > - val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0); > val |= NPCM7XX_START_ONESHOT_Tx; > writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0); > > @@ -97,12 +95,11 @@ static int npcm7xx_timer_periodic(struct > clock_event_device *evt) Your mail client mangled the patch so it does not apply: patching file drivers/clocksource/timer-npcm7xx.c Hunk #1 FAILED at 32. patch: **** malformed patch at line 49: clock_event_device *evt) See Documentation/process for hints about sending patches with various mail clients. Send the patch to yourself first and try to apply it yourself. Thanks, tglx
diff --git a/drivers/clocksource/timer-npcm7xx.c b/drivers/clocksource/timer-npcm7xx.c index 8a30da7f083b..9780ffd8010e 100644 --- a/drivers/clocksource/timer-npcm7xx.c +++ b/drivers/clocksource/timer-npcm7xx.c @@ -32,7 +32,7 @@ #define NPCM7XX_Tx_INTEN BIT(29) #define NPCM7XX_Tx_COUNTEN BIT(30) #define NPCM7XX_Tx_ONESHOT 0x0 -#define NPCM7XX_Tx_OPER GENMASK(27, 3) +#define NPCM7XX_Tx_OPER GENMASK(28, 27) #define NPCM7XX_Tx_MIN_PRESCALE 0x1 #define NPCM7XX_Tx_TDR_MASK_BITS 24 #define NPCM7XX_Tx_MAX_CNT 0xFFFFFF @@ -84,8 +84,6 @@ static int npcm7xx_timer_oneshot(struct clock_event_device *evt) val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0); val &= ~NPCM7XX_Tx_OPER; - - val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0); val |= NPCM7XX_START_ONESHOT_Tx; writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
clocksource/drivers/npcm: fix GENMASK and timer operation NPCM7XX_Tx_OPER GENMASK() changed from (27, 3) to (28, 27) Since NPCM7XX_REG_TICR0 register reset value of those bits was 0, it did not cause an issue in npcm7xx_timer_oneshot() the original NPCM7XX_REG_TCSR0 register was read again after masking it with ~NPCM7XX_Tx_OPER so the masking didn't take effect. npcm7xx_timer_periodic() was not wrong but it wrote to NPCM7XX_REG_TICR0 in a middle of read modify write to NPCM7XX_REG_TCSR0 which is confusing. Signed-off-by: Avi Fishman <avifishman70@gmail.com> --- drivers/clocksource/timer-npcm7xx.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) @@ -97,12 +95,11 @@ static int npcm7xx_timer_periodic(struct clock_event_device *evt) struct timer_of *to = to_timer_of(evt); u32 val; + writel(timer_of_period(to), timer_of_base(to) + NPCM7XX_REG_TICR0); + val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0); val &= ~NPCM7XX_Tx_OPER; - - writel(timer_of_period(to), timer_of_base(to) + NPCM7XX_REG_TICR0); val |= NPCM7XX_START_PERIODIC_Tx; - writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0); return 0;