| Message ID | 20190623104152.13173-1-npiggin@gmail.com |
|---|---|
| State | Accepted |
| Headers | show |
| Series | [1/2] powerpc/64s: Rename PPC_INVALIDATE_ERAT to PPC_ARCH_300_INVALIDATE_ERAT | expand |
On Sun, Jun 23, 2019 at 08:41:51PM +1000, Nicholas Piggin wrote: > This makes it clear to the caller that it can only be used on POWER9 > and later CPUs. > -#define PPC_INVALIDATE_ERAT PPC_SLBIA(7) > +#define PPC_ARCH_300_INVALIDATE_ERAT PPC_SLBIA(7) The architecture version is 3.0 (or 3.0B), not "300". This will work on implementations of later architecture versions as well, so maybe the name isn't so great anyway? Segher
Segher Boessenkool's on June 23, 2019 10:03 pm: > On Sun, Jun 23, 2019 at 08:41:51PM +1000, Nicholas Piggin wrote: >> This makes it clear to the caller that it can only be used on POWER9 >> and later CPUs. > >> -#define PPC_INVALIDATE_ERAT PPC_SLBIA(7) >> +#define PPC_ARCH_300_INVALIDATE_ERAT PPC_SLBIA(7) > > The architecture version is 3.0 (or 3.0B), not "300". This will work on > implementations of later architecture versions as well, so maybe the name > isn't so great anyway? Yeah... this is kernel convention for better or worse. ISA v3.0B feature support is called CPU_FTR_ARCH_300, and later architectures will advertise that support. For the most part we can use architected features (incompatible changes would require additional code). Thanks, Nick
Nicholas Piggin <npiggin@gmail.com> writes: > Segher Boessenkool's on June 23, 2019 10:03 pm: >> On Sun, Jun 23, 2019 at 08:41:51PM +1000, Nicholas Piggin wrote: >>> This makes it clear to the caller that it can only be used on POWER9 >>> and later CPUs. >> >>> -#define PPC_INVALIDATE_ERAT PPC_SLBIA(7) >>> +#define PPC_ARCH_300_INVALIDATE_ERAT PPC_SLBIA(7) >> >> The architecture version is 3.0 (or 3.0B), not "300". This will work on >> implementations of later architecture versions as well, so maybe the name >> isn't so great anyway? > > Yeah... this is kernel convention for better or worse. ISA v3.0B > feature support is called CPU_FTR_ARCH_300, and later architectures > will advertise that support. For the most part we can use architected > features (incompatible changes would require additional code). I'd rather we used 3_0B or something inside the kernel, but I'm not sure it's worth the churn to rename the existing feature everywhere. And we can't rename the user visible feature. But if you're adding a new usage then I'd prefer: PPC_ISA_3_0B_INVALIDATE_ERAT I dislike "300" because it implies we support ISA v3.0 but we actually don't, we only support v3.0B. cheers
On Sun, 2019-06-23 at 10:41:51 UTC, Nicholas Piggin wrote: > This makes it clear to the caller that it can only be used on POWER9 > and later CPUs. > > Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Series applied to powerpc next, thanks. https://git.kernel.org/powerpc/c/fe7946ce0808eb0e43711f5db7d2d1599b362d02 cheers
diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h index 2291daf39cd1..156102828a3b 100644 --- a/arch/powerpc/include/asm/ppc-opcode.h +++ b/arch/powerpc/include/asm/ppc-opcode.h @@ -588,7 +588,7 @@ #define PPC_SLBIA(IH) stringify_in_c(.long PPC_INST_SLBIA | \ ((IH & 0x7) << 21)) -#define PPC_INVALIDATE_ERAT PPC_SLBIA(7) +#define PPC_ARCH_300_INVALIDATE_ERAT PPC_SLBIA(7) #define VCMPEQUD_RC(vrt, vra, vrb) stringify_in_c(.long PPC_INST_VCMPEQUD | \ ___PPC_RT(vrt) | ___PPC_RA(vra) | \ diff --git a/arch/powerpc/kernel/mce_power.c b/arch/powerpc/kernel/mce_power.c index e39536aad30d..91e20773d8c3 100644 --- a/arch/powerpc/kernel/mce_power.c +++ b/arch/powerpc/kernel/mce_power.c @@ -82,8 +82,7 @@ static void flush_erat(void) return; } #endif - /* PPC_INVALIDATE_ERAT can only be used on ISA v3 and newer */ - asm volatile(PPC_INVALIDATE_ERAT : : :"memory"); + asm volatile(PPC_ARCH_300_INVALIDATE_ERAT : : :"memory"); } #define MCE_FLUSH_SLB 1 diff --git a/arch/powerpc/kvm/book3s_hv_builtin.c b/arch/powerpc/kvm/book3s_hv_builtin.c index cb05ccc8bc6a..960154262665 100644 --- a/arch/powerpc/kvm/book3s_hv_builtin.c +++ b/arch/powerpc/kvm/book3s_hv_builtin.c @@ -830,7 +830,7 @@ static void flush_guest_tlb(struct kvm *kvm) } } asm volatile("ptesync": : :"memory"); - asm volatile(PPC_INVALIDATE_ERAT : : :"memory"); + asm volatile(PPC_ARCH_300_INVALIDATE_ERAT : : :"memory"); } void kvmppc_check_need_tlb_flush(struct kvm *kvm, int pcpu, diff --git a/arch/powerpc/mm/book3s64/hash_native.c b/arch/powerpc/mm/book3s64/hash_native.c index 30d62ffe3310..55a1716926b1 100644 --- a/arch/powerpc/mm/book3s64/hash_native.c +++ b/arch/powerpc/mm/book3s64/hash_native.c @@ -112,7 +112,7 @@ static void tlbiel_all_isa300(unsigned int num_sets, unsigned int is) asm volatile("ptesync": : :"memory"); - asm volatile(PPC_INVALIDATE_ERAT "; isync" : : :"memory"); + asm volatile(PPC_ARCH_300_INVALIDATE_ERAT "; isync" : : :"memory"); } void hash__tlbiel_all(unsigned int action) diff --git a/arch/powerpc/mm/book3s64/radix_tlb.c b/arch/powerpc/mm/book3s64/radix_tlb.c index bb9835681315..17f33b6645f9 100644 --- a/arch/powerpc/mm/book3s64/radix_tlb.c +++ b/arch/powerpc/mm/book3s64/radix_tlb.c @@ -83,7 +83,7 @@ void radix__tlbiel_all(unsigned int action) else WARN(1, "%s called on pre-POWER9 CPU\n", __func__); - asm volatile(PPC_INVALIDATE_ERAT "; isync" : : :"memory"); + asm volatile(PPC_ARCH_300_INVALIDATE_ERAT "; isync" : : :"memory"); } static __always_inline void __tlbiel_pid(unsigned long pid, int set, @@ -258,7 +258,7 @@ static inline void _tlbiel_pid(unsigned long pid, unsigned long ric) __tlbiel_pid(pid, set, RIC_FLUSH_TLB); asm volatile("ptesync": : :"memory"); - asm volatile(PPC_INVALIDATE_ERAT "; isync" : : :"memory"); + asm volatile(PPC_ARCH_300_INVALIDATE_ERAT "; isync" : : :"memory"); } static inline void _tlbie_pid(unsigned long pid, unsigned long ric) @@ -310,7 +310,7 @@ static inline void _tlbiel_lpid(unsigned long lpid, unsigned long ric) __tlbiel_lpid(lpid, set, RIC_FLUSH_TLB); asm volatile("ptesync": : :"memory"); - asm volatile(PPC_INVALIDATE_ERAT "; isync" : : :"memory"); + asm volatile(PPC_ARCH_300_INVALIDATE_ERAT "; isync" : : :"memory"); } static inline void _tlbie_lpid(unsigned long lpid, unsigned long ric) @@ -362,7 +362,7 @@ static inline void _tlbiel_lpid_guest(unsigned long lpid, unsigned long ric) __tlbiel_lpid_guest(lpid, set, RIC_FLUSH_TLB); asm volatile("ptesync": : :"memory"); - asm volatile(PPC_INVALIDATE_ERAT : : :"memory"); + asm volatile(PPC_ARCH_300_INVALIDATE_ERAT : : :"memory"); } diff --git a/arch/powerpc/platforms/powernv/idle.c b/arch/powerpc/platforms/powernv/idle.c index 2f4479b94ac3..fea2fab6d915 100644 --- a/arch/powerpc/platforms/powernv/idle.c +++ b/arch/powerpc/platforms/powernv/idle.c @@ -716,7 +716,7 @@ static unsigned long power9_idle_stop(unsigned long psscr, bool mmu_on) * to reload MMCR0 (see mmcr0 comment above). */ if (!cpu_has_feature(CPU_FTR_POWER9_DD2_1)) { - asm volatile(PPC_INVALIDATE_ERAT); + asm volatile(PPC_ARCH_300_INVALIDATE_ERAT); mtspr(SPRN_MMCR0, mmcr0); }
This makes it clear to the caller that it can only be used on POWER9 and later CPUs. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> --- I think I added a bug in machine checks at one point that I might have been able to avoid with this name :) arch/powerpc/include/asm/ppc-opcode.h | 2 +- arch/powerpc/kernel/mce_power.c | 3 +-- arch/powerpc/kvm/book3s_hv_builtin.c | 2 +- arch/powerpc/mm/book3s64/hash_native.c | 2 +- arch/powerpc/mm/book3s64/radix_tlb.c | 8 ++++---- arch/powerpc/platforms/powernv/idle.c | 2 +- 6 files changed, 9 insertions(+), 10 deletions(-)