| Message ID | 20190624091505.1711-1-vidyas@nvidia.com |
|---|---|
| Headers | show |
| Series | Add Tegra194 PCIe support | expand |
On Mon, Jun 24, 2019 at 02:44:54PM +0530, Vidya Sagar wrote: > Add #defines only for the Data Link Feature and Physical Layer 16.0 GT/s > features. > > Signed-off-by: Vidya Sagar <vidyas@nvidia.com> > Reviewed-by: Thierry Reding <treding@nvidia.com> > --- > Changes since [v10]: > * None > > Changes since [v9]: > * None > > Changes since [v8]: > * None > > Changes since [v7]: > * None > > Changes since [v6]: > * None > > Changes since [v5]: > * None > > Changes since [v4]: > * None > > Changes since [v3]: > * None > > Changes since [v2]: > * Updated commit message and description to explicitly mention that defines are > added only for some of the features and not all. > > Changes since [v1]: > * None > > include/uapi/linux/pci_regs.h | 22 +++++++++++++++++++++- > 1 file changed, 21 insertions(+), 1 deletion(-) I need Bjorn's ACK to merge this patch. Lorenzo > diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h > index f28e562d7ca8..1c79f6a097d2 100644 > --- a/include/uapi/linux/pci_regs.h > +++ b/include/uapi/linux/pci_regs.h > @@ -713,7 +713,9 @@ > #define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */ > #define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */ > #define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */ > -#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PTM > +#define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */ > +#define PCI_EXT_CAP_ID_PL 0x26 /* Physical Layer 16.0 GT/s */ > +#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PL > > #define PCI_EXT_CAP_DSN_SIZEOF 12 > #define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40 > @@ -1053,4 +1055,22 @@ > #define PCI_L1SS_CTL1_LTR_L12_TH_SCALE 0xe0000000 /* LTR_L1.2_THRESHOLD_Scale */ > #define PCI_L1SS_CTL2 0x0c /* Control 2 Register */ > > +/* Data Link Feature */ > +#define PCI_DLF_CAP 0x04 /* Capabilities Register */ > +#define PCI_DLF_LOCAL_DLF_SUP_MASK 0x007fffff /* Local Data Link Feature Supported */ > +#define PCI_DLF_EXCHANGE_ENABLE 0x80000000 /* Data Link Feature Exchange Enable */ > +#define PCI_DLF_STS 0x08 /* Status Register */ > +#define PCI_DLF_REMOTE_DLF_SUP_MASK 0x007fffff /* Remote Data Link Feature Supported */ > +#define PCI_DLF_REMOTE_DLF_SUP_VALID 0x80000000 /* Remote Data Link Feature Support Valid */ > + > +/* Physical Layer 16.0 GT/s */ > +#define PCI_PL_16GT_CAP 0x04 /* Capabilities Register */ > +#define PCI_PL_16GT_CTRL 0x08 /* Control Register */ > +#define PCI_PL_16GT_STS 0x0c /* Status Register */ > +#define PCI_PL_16GT_LDPM_STS 0x10 /* Local Data Parity Mismatch Status Register */ > +#define PCI_PL_16GT_FRDPM_STS 0x14 /* First Retimer Data Parity Mismatch Status Register */ > +#define PCI_PL_16GT_SRDPM_STS 0x18 /* Second Retimer Data Parity Mismatch Status Register */ > +#define PCI_PL_16GT_RSVD 0x1C /* Reserved */ > +#define PCI_PL_16GT_LE_CTRL 0x20 /* Lane Equalization Control Register */ > + > #endif /* LINUX_PCI_REGS_H */ > -- > 2.17.1 >
On Mon, Jun 24, 2019 at 02:44:56PM +0530, Vidya Sagar wrote: > Remove multiple write enable and disable sequences of dbi registers as > Tegra194 implements writes to BAR-0 register (offset: 0x10) controlled by > DBI write-lock enable bit thereby not allowing any further writes to BAR-0 > register in config space to take place. Hence enabling write permission at > the start of function and disabling the same only towards the end. I do not understand what this patch does, I would like to rephrase the commit log in a way that is easier to parse. In particular I do not get what you mean in relation to BAR-0, I am confused, please clarify. Lorenzo > Signed-off-by: Vidya Sagar <vidyas@nvidia.com> > Reviewed-by: Thierry Reding <treding@nvidia.com> > Acked-by: Jingoo Han <jingoohan1@gmail.com> > --- > Changes since [v10]: > * None > > Changes since [v9]: > * None > > Changes since [v8]: > * None > > Changes since [v7]: > * None > > Changes since [v6]: > * None > > Changes since [v5]: > * Moved write enable to the beginning of the API and write disable to the end > > Changes since [v4]: > * None > > Changes since [v3]: > * None > > Changes since [v2]: > * None > > Changes since [v1]: > * None > > drivers/pci/controller/dwc/pcie-designware-host.c | 14 ++++++++------ > 1 file changed, 8 insertions(+), 6 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c > index f93252d0da5b..d3156446ff27 100644 > --- a/drivers/pci/controller/dwc/pcie-designware-host.c > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c > @@ -628,6 +628,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp) > u32 val, ctrl, num_ctrls; > struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > > + /* > + * Enable DBI read-only registers for writing/updating configuration. > + * Write permission gets disabled towards the end of this function. > + */ > + dw_pcie_dbi_ro_wr_en(pci); > + > dw_pcie_setup(pci); > > if (!pp->ops->msi_host_init) { > @@ -650,12 +656,10 @@ void dw_pcie_setup_rc(struct pcie_port *pp) > dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000); > > /* Setup interrupt pins */ > - dw_pcie_dbi_ro_wr_en(pci); > val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE); > val &= 0xffff00ff; > val |= 0x00000100; > dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val); > - dw_pcie_dbi_ro_wr_dis(pci); > > /* Setup bus numbers */ > val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS); > @@ -687,15 +691,13 @@ void dw_pcie_setup_rc(struct pcie_port *pp) > > dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0); > > - /* Enable write permission for the DBI read-only register */ > - dw_pcie_dbi_ro_wr_en(pci); > /* Program correct class for RC */ > dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI); > - /* Better disable write permission right after the update */ > - dw_pcie_dbi_ro_wr_dis(pci); > > dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val); > val |= PORT_LOGIC_SPEED_CHANGE; > dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val); > + > + dw_pcie_dbi_ro_wr_dis(pci); > } > EXPORT_SYMBOL_GPL(dw_pcie_setup_rc); > -- > 2.17.1 >
On 6/27/2019 8:28 PM, Lorenzo Pieralisi wrote: > On Mon, Jun 24, 2019 at 02:44:56PM +0530, Vidya Sagar wrote: >> Remove multiple write enable and disable sequences of dbi registers as >> Tegra194 implements writes to BAR-0 register (offset: 0x10) controlled by >> DBI write-lock enable bit thereby not allowing any further writes to BAR-0 >> register in config space to take place. Hence enabling write permission at >> the start of function and disabling the same only towards the end. > > I do not understand what this patch does, I would like to rephrase > the commit log in a way that is easier to parse. > > In particular I do not get what you mean in relation to BAR-0, I am > confused, please clarify. > > Lorenzo Well, some of the Synopsys DesignWare core's DBI registers are protected with a lock without which, they are read-only by default. Existing code in dw_pcie_setup_rc() API tries to unlock and lock multiple times whenever it wants to update those write-protected registers. This patch attempts to unlock all such write-protected registers for writing once in the beginning of the function and lock them back towards the end. As far as BAR-0 register (which is at offset 0x10 in DBI space... nothing but the config space) in Tegra194 is concerned, it is one of those registers to which writes are protected. I could have added unlock/lock pair around accessing this register, but that would bloat this API with one more pair of unlock/lock, instead I chose to remove unlock/lock pairs for all protected registers and have unlock in the beginning and lock towards the end. -Vidya Sagar > >> Signed-off-by: Vidya Sagar <vidyas@nvidia.com> >> Reviewed-by: Thierry Reding <treding@nvidia.com> >> Acked-by: Jingoo Han <jingoohan1@gmail.com> >> --- >> Changes since [v10]: >> * None >> >> Changes since [v9]: >> * None >> >> Changes since [v8]: >> * None >> >> Changes since [v7]: >> * None >> >> Changes since [v6]: >> * None >> >> Changes since [v5]: >> * Moved write enable to the beginning of the API and write disable to the end >> >> Changes since [v4]: >> * None >> >> Changes since [v3]: >> * None >> >> Changes since [v2]: >> * None >> >> Changes since [v1]: >> * None >> >> drivers/pci/controller/dwc/pcie-designware-host.c | 14 ++++++++------ >> 1 file changed, 8 insertions(+), 6 deletions(-) >> >> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c >> index f93252d0da5b..d3156446ff27 100644 >> --- a/drivers/pci/controller/dwc/pcie-designware-host.c >> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c >> @@ -628,6 +628,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp) >> u32 val, ctrl, num_ctrls; >> struct dw_pcie *pci = to_dw_pcie_from_pp(pp); >> >> + /* >> + * Enable DBI read-only registers for writing/updating configuration. >> + * Write permission gets disabled towards the end of this function. >> + */ >> + dw_pcie_dbi_ro_wr_en(pci); >> + >> dw_pcie_setup(pci); >> >> if (!pp->ops->msi_host_init) { >> @@ -650,12 +656,10 @@ void dw_pcie_setup_rc(struct pcie_port *pp) >> dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000); >> >> /* Setup interrupt pins */ >> - dw_pcie_dbi_ro_wr_en(pci); >> val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE); >> val &= 0xffff00ff; >> val |= 0x00000100; >> dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val); >> - dw_pcie_dbi_ro_wr_dis(pci); >> >> /* Setup bus numbers */ >> val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS); >> @@ -687,15 +691,13 @@ void dw_pcie_setup_rc(struct pcie_port *pp) >> >> dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0); >> >> - /* Enable write permission for the DBI read-only register */ >> - dw_pcie_dbi_ro_wr_en(pci); >> /* Program correct class for RC */ >> dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI); >> - /* Better disable write permission right after the update */ >> - dw_pcie_dbi_ro_wr_dis(pci); >> >> dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val); >> val |= PORT_LOGIC_SPEED_CHANGE; >> dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val); >> + >> + dw_pcie_dbi_ro_wr_dis(pci); >> } >> EXPORT_SYMBOL_GPL(dw_pcie_setup_rc); >> -- >> 2.17.1 >>
On Thu, Jun 27, 2019 at 09:03:08PM +0530, Vidya Sagar wrote: > On 6/27/2019 8:28 PM, Lorenzo Pieralisi wrote: > > On Mon, Jun 24, 2019 at 02:44:56PM +0530, Vidya Sagar wrote: > > > Remove multiple write enable and disable sequences of dbi registers as > > > Tegra194 implements writes to BAR-0 register (offset: 0x10) controlled by > > > DBI write-lock enable bit thereby not allowing any further writes to BAR-0 > > > register in config space to take place. Hence enabling write permission at > > > the start of function and disabling the same only towards the end. > > > > I do not understand what this patch does, I would like to rephrase > > the commit log in a way that is easier to parse. > > > > In particular I do not get what you mean in relation to BAR-0, I am > > confused, please clarify. > > > > Lorenzo > Well, some of the Synopsys DesignWare core's DBI registers are > protected with a lock without which, they are read-only by default. > Existing code in dw_pcie_setup_rc() API tries to unlock and lock > multiple times whenever it wants to update those write-protected > registers. This patch attempts to unlock all such write-protected > registers for writing once in the beginning of the function and lock > them back towards the end. As far as BAR-0 register (which is at > offset 0x10 in DBI space... nothing but the config space) in Tegra194 > is concerned, it is one of those registers to which writes are > protected. I could have added unlock/lock pair around accessing this > register, but that would bloat this API with one more pair of > unlock/lock, instead I chose to remove unlock/lock pairs for all > protected registers and have unlock in the beginning and lock towards > the end. Ok, so DBI space registers that require write permissions are per-IP. This is clearer so the commit log must be rewritten, it is not clear at all in this respect at least not as-is, if you read it you will notice ;-) Lorenzo > > -Vidya Sagar > > > > > > Signed-off-by: Vidya Sagar <vidyas@nvidia.com> > > > Reviewed-by: Thierry Reding <treding@nvidia.com> > > > Acked-by: Jingoo Han <jingoohan1@gmail.com> > > > --- > > > Changes since [v10]: > > > * None > > > > > > Changes since [v9]: > > > * None > > > > > > Changes since [v8]: > > > * None > > > > > > Changes since [v7]: > > > * None > > > > > > Changes since [v6]: > > > * None > > > > > > Changes since [v5]: > > > * Moved write enable to the beginning of the API and write disable to the end > > > > > > Changes since [v4]: > > > * None > > > > > > Changes since [v3]: > > > * None > > > > > > Changes since [v2]: > > > * None > > > > > > Changes since [v1]: > > > * None > > > > > > drivers/pci/controller/dwc/pcie-designware-host.c | 14 ++++++++------ > > > 1 file changed, 8 insertions(+), 6 deletions(-) > > > > > > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c > > > index f93252d0da5b..d3156446ff27 100644 > > > --- a/drivers/pci/controller/dwc/pcie-designware-host.c > > > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c > > > @@ -628,6 +628,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp) > > > u32 val, ctrl, num_ctrls; > > > struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > > > + /* > > > + * Enable DBI read-only registers for writing/updating configuration. > > > + * Write permission gets disabled towards the end of this function. > > > + */ > > > + dw_pcie_dbi_ro_wr_en(pci); > > > + > > > dw_pcie_setup(pci); > > > if (!pp->ops->msi_host_init) { > > > @@ -650,12 +656,10 @@ void dw_pcie_setup_rc(struct pcie_port *pp) > > > dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000); > > > /* Setup interrupt pins */ > > > - dw_pcie_dbi_ro_wr_en(pci); > > > val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE); > > > val &= 0xffff00ff; > > > val |= 0x00000100; > > > dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val); > > > - dw_pcie_dbi_ro_wr_dis(pci); > > > /* Setup bus numbers */ > > > val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS); > > > @@ -687,15 +691,13 @@ void dw_pcie_setup_rc(struct pcie_port *pp) > > > dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0); > > > - /* Enable write permission for the DBI read-only register */ > > > - dw_pcie_dbi_ro_wr_en(pci); > > > /* Program correct class for RC */ > > > dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI); > > > - /* Better disable write permission right after the update */ > > > - dw_pcie_dbi_ro_wr_dis(pci); > > > dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val); > > > val |= PORT_LOGIC_SPEED_CHANGE; > > > dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val); > > > + > > > + dw_pcie_dbi_ro_wr_dis(pci); > > > } > > > EXPORT_SYMBOL_GPL(dw_pcie_setup_rc); > > > -- > > > 2.17.1 > > > >
On 6/27/2019 9:20 PM, Lorenzo Pieralisi wrote: > On Thu, Jun 27, 2019 at 09:03:08PM +0530, Vidya Sagar wrote: >> On 6/27/2019 8:28 PM, Lorenzo Pieralisi wrote: >>> On Mon, Jun 24, 2019 at 02:44:56PM +0530, Vidya Sagar wrote: >>>> Remove multiple write enable and disable sequences of dbi registers as >>>> Tegra194 implements writes to BAR-0 register (offset: 0x10) controlled by >>>> DBI write-lock enable bit thereby not allowing any further writes to BAR-0 >>>> register in config space to take place. Hence enabling write permission at >>>> the start of function and disabling the same only towards the end. >>> >>> I do not understand what this patch does, I would like to rephrase >>> the commit log in a way that is easier to parse. >>> >>> In particular I do not get what you mean in relation to BAR-0, I am >>> confused, please clarify. >>> >>> Lorenzo >> Well, some of the Synopsys DesignWare core's DBI registers are >> protected with a lock without which, they are read-only by default. >> Existing code in dw_pcie_setup_rc() API tries to unlock and lock >> multiple times whenever it wants to update those write-protected >> registers. This patch attempts to unlock all such write-protected >> registers for writing once in the beginning of the function and lock >> them back towards the end. As far as BAR-0 register (which is at >> offset 0x10 in DBI space... nothing but the config space) in Tegra194 >> is concerned, it is one of those registers to which writes are >> protected. I could have added unlock/lock pair around accessing this >> register, but that would bloat this API with one more pair of >> unlock/lock, instead I chose to remove unlock/lock pairs for all >> protected registers and have unlock in the beginning and lock towards >> the end. > > Ok, so DBI space registers that require write permissions are per-IP. > This is clearer so the commit log must be rewritten, it is not clear at > all in this respect at least not as-is, if you read it you will > notice ;-) Ok. I'll update commit message in next patch series. -Vidya Sagar > > Lorenzo > >> >> -Vidya Sagar >> >>> >>>> Signed-off-by: Vidya Sagar <vidyas@nvidia.com> >>>> Reviewed-by: Thierry Reding <treding@nvidia.com> >>>> Acked-by: Jingoo Han <jingoohan1@gmail.com> >>>> --- >>>> Changes since [v10]: >>>> * None >>>> >>>> Changes since [v9]: >>>> * None >>>> >>>> Changes since [v8]: >>>> * None >>>> >>>> Changes since [v7]: >>>> * None >>>> >>>> Changes since [v6]: >>>> * None >>>> >>>> Changes since [v5]: >>>> * Moved write enable to the beginning of the API and write disable to the end >>>> >>>> Changes since [v4]: >>>> * None >>>> >>>> Changes since [v3]: >>>> * None >>>> >>>> Changes since [v2]: >>>> * None >>>> >>>> Changes since [v1]: >>>> * None >>>> >>>> drivers/pci/controller/dwc/pcie-designware-host.c | 14 ++++++++------ >>>> 1 file changed, 8 insertions(+), 6 deletions(-) >>>> >>>> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c >>>> index f93252d0da5b..d3156446ff27 100644 >>>> --- a/drivers/pci/controller/dwc/pcie-designware-host.c >>>> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c >>>> @@ -628,6 +628,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp) >>>> u32 val, ctrl, num_ctrls; >>>> struct dw_pcie *pci = to_dw_pcie_from_pp(pp); >>>> + /* >>>> + * Enable DBI read-only registers for writing/updating configuration. >>>> + * Write permission gets disabled towards the end of this function. >>>> + */ >>>> + dw_pcie_dbi_ro_wr_en(pci); >>>> + >>>> dw_pcie_setup(pci); >>>> if (!pp->ops->msi_host_init) { >>>> @@ -650,12 +656,10 @@ void dw_pcie_setup_rc(struct pcie_port *pp) >>>> dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000); >>>> /* Setup interrupt pins */ >>>> - dw_pcie_dbi_ro_wr_en(pci); >>>> val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE); >>>> val &= 0xffff00ff; >>>> val |= 0x00000100; >>>> dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val); >>>> - dw_pcie_dbi_ro_wr_dis(pci); >>>> /* Setup bus numbers */ >>>> val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS); >>>> @@ -687,15 +691,13 @@ void dw_pcie_setup_rc(struct pcie_port *pp) >>>> dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0); >>>> - /* Enable write permission for the DBI read-only register */ >>>> - dw_pcie_dbi_ro_wr_en(pci); >>>> /* Program correct class for RC */ >>>> dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI); >>>> - /* Better disable write permission right after the update */ >>>> - dw_pcie_dbi_ro_wr_dis(pci); >>>> dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val); >>>> val |= PORT_LOGIC_SPEED_CHANGE; >>>> dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val); >>>> + >>>> + dw_pcie_dbi_ro_wr_dis(pci); >>>> } >>>> EXPORT_SYMBOL_GPL(dw_pcie_setup_rc); >>>> -- >>>> 2.17.1 >>>> >>
On 6/27/2019 8:08 PM, Lorenzo Pieralisi wrote: > On Mon, Jun 24, 2019 at 02:44:54PM +0530, Vidya Sagar wrote: >> Add #defines only for the Data Link Feature and Physical Layer 16.0 GT/s >> features. >> >> Signed-off-by: Vidya Sagar <vidyas@nvidia.com> >> Reviewed-by: Thierry Reding <treding@nvidia.com> >> --- >> Changes since [v10]: >> * None >> >> Changes since [v9]: >> * None >> >> Changes since [v8]: >> * None >> >> Changes since [v7]: >> * None >> >> Changes since [v6]: >> * None >> >> Changes since [v5]: >> * None >> >> Changes since [v4]: >> * None >> >> Changes since [v3]: >> * None >> >> Changes since [v2]: >> * Updated commit message and description to explicitly mention that defines are >> added only for some of the features and not all. >> >> Changes since [v1]: >> * None >> >> include/uapi/linux/pci_regs.h | 22 +++++++++++++++++++++- >> 1 file changed, 21 insertions(+), 1 deletion(-) > > I need Bjorn's ACK to merge this patch. I sent V12 patches out for review. Bjorn, please provide ACK for V12 version of this change. -Vidya Sagar > > Lorenzo > >> diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h >> index f28e562d7ca8..1c79f6a097d2 100644 >> --- a/include/uapi/linux/pci_regs.h >> +++ b/include/uapi/linux/pci_regs.h >> @@ -713,7 +713,9 @@ >> #define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */ >> #define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */ >> #define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */ >> -#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PTM >> +#define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */ >> +#define PCI_EXT_CAP_ID_PL 0x26 /* Physical Layer 16.0 GT/s */ >> +#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PL >> >> #define PCI_EXT_CAP_DSN_SIZEOF 12 >> #define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40 >> @@ -1053,4 +1055,22 @@ >> #define PCI_L1SS_CTL1_LTR_L12_TH_SCALE 0xe0000000 /* LTR_L1.2_THRESHOLD_Scale */ >> #define PCI_L1SS_CTL2 0x0c /* Control 2 Register */ >> >> +/* Data Link Feature */ >> +#define PCI_DLF_CAP 0x04 /* Capabilities Register */ >> +#define PCI_DLF_LOCAL_DLF_SUP_MASK 0x007fffff /* Local Data Link Feature Supported */ >> +#define PCI_DLF_EXCHANGE_ENABLE 0x80000000 /* Data Link Feature Exchange Enable */ >> +#define PCI_DLF_STS 0x08 /* Status Register */ >> +#define PCI_DLF_REMOTE_DLF_SUP_MASK 0x007fffff /* Remote Data Link Feature Supported */ >> +#define PCI_DLF_REMOTE_DLF_SUP_VALID 0x80000000 /* Remote Data Link Feature Support Valid */ >> + >> +/* Physical Layer 16.0 GT/s */ >> +#define PCI_PL_16GT_CAP 0x04 /* Capabilities Register */ >> +#define PCI_PL_16GT_CTRL 0x08 /* Control Register */ >> +#define PCI_PL_16GT_STS 0x0c /* Status Register */ >> +#define PCI_PL_16GT_LDPM_STS 0x10 /* Local Data Parity Mismatch Status Register */ >> +#define PCI_PL_16GT_FRDPM_STS 0x14 /* First Retimer Data Parity Mismatch Status Register */ >> +#define PCI_PL_16GT_SRDPM_STS 0x18 /* Second Retimer Data Parity Mismatch Status Register */ >> +#define PCI_PL_16GT_RSVD 0x1C /* Reserved */ >> +#define PCI_PL_16GT_LE_CTRL 0x20 /* Lane Equalization Control Register */ >> + >> #endif /* LINUX_PCI_REGS_H */ >> -- >> 2.17.1 >>