mbox series

[V8,00/15] Add Tegra194 PCIe support

Message ID 20190526043751.12729-1-vidyas@nvidia.com
Headers show
Series Add Tegra194 PCIe support | expand

Message

Vidya Sagar May 26, 2019, 4:37 a.m. UTC
Tegra194 has six PCIe controllers based on Synopsys DesignWare core.
There are two Universal PHY (UPHY) blocks with each supporting 12(HSIO:
Hisg Speed IO) and 8(NVHS: NVIDIA High Speed) lanes respectively.
Controllers:0~4 use UPHY lanes from HSIO brick whereas Controller:5 uses
UPHY lanes from NVHS brick. Lane mapping in HSIO UPHY brick to each PCIe
controller (0~4) is controlled in XBAR module by BPMP-FW. Since PCIe
core has PIPE interface, a glue module called PIPE-to-UPHY (P2U) is used
to connect each UPHY lane (applicable to both HSIO and NVHS UPHY bricks)
to PCIe controller
This patch series
- Adds support for P2U PHY driver
- Adds support for PCIe host controller
- Adds device tree nodes each PCIe controllers
- Enables nodes applicable to p2972-0000 platform
- Adds helper APIs in Designware core driver to get capability regs offset
- Adds defines for new feature registers of PCIe spec revision 4
- Makes changes in DesignWare core driver to get Tegra194 PCIe working

Testing done on P2972-0000 platform
- Able to get PCIe link up with on-board Marvel eSATA controller
- Able to get PCIe link up with NVMe cards connected to M.2 Key-M slot
- Able to do data transfers with both SATA drives and NVMe cards

Note
- Enabling x8 slot on P2972-0000 platform requires pinmux driver for Tegra194.
  It is being worked on currently and hence Controller:5 (i.e. x8 slot) is
  disabled in this patch series. A future patch series would enable this.
- This series is based on top of the following series
  Jisheng's patches to add support to .remove() in Designware sub-system
  https://patchwork.kernel.org/project/linux-pci/list/?series=98559
  (Jisheng's patches are now accepted and applied for v5.2)
  My patches made on top of Jisheng's patches to export various symbols
  https://patchwork.kernel.org/project/linux-pci/list/?series=101259

Changes since [v7]:
* Changed P2U driver file name from pcie-p2u-tegra194.c to phy-tegra194-p2u.c
* Addressed review comments from Thierry and Rob

Changes since [v6]:
* Took care of review comments from Rob
* Added a quirk to disable MSI for root ports
* Removed using pcie_pme_disable_msi() API in host controller driver

Changes since [v5]:
* Removed patch that exports pcie_bus_config symbol
* Took care of review comments from Thierry and Rob

Changes since [v4]:
* Removed redundant APIs in pcie-designware-ep.c file after moving them
  to pcie-designware.c file based on Bjorn's review comments

Changes since [v3]:
* Rebased on top of linux-next top of the tree
* Addressed Gustavo's comments and added his Ack for some of the changes.

Changes since [v2]:
* Addressed review comments from Thierry

Changes since [v1]:
* Addressed review comments from Bjorn, Thierry, Jonathan, Rob & Kishon
* Added more patches in v2 series

Vidya Sagar (15):
  PCI: Add #defines for some of PCIe spec r4.0 features
  PCI: Disable MSI for Tegra194 root port
  PCI: dwc: Perform dbi regs write lock towards the end
  PCI: dwc: Move config space capability search API
  PCI: dwc: Add ext config space capability search API
  dt-bindings: PCI: designware: Add binding for CDM register check
  PCI: dwc: Add support to enable CDM register check
  dt-bindings: Add PCIe supports-clkreq property
  dt-bindings: PCI: tegra: Add device tree support for Tegra194
  dt-bindings: PHY: P2U: Add Tegra194 P2U block
  arm64: tegra: Add P2U and PCIe controller nodes to Tegra194 DT
  arm64: tegra: Enable PCIe slots in P2972-0000 board
  phy: tegra: Add PCIe PIPE2UPHY support
  PCI: tegra: Add Tegra194 PCIe support
  arm64: Add Tegra194 PCIe driver to defconfig

 .../bindings/pci/designware-pcie.txt          |    5 +
 .../bindings/pci/nvidia,tegra194-pcie.txt     |  155 ++
 Documentation/devicetree/bindings/pci/pci.txt |    5 +
 .../bindings/phy/phy-tegra194-p2u.txt         |   28 +
 .../arm64/boot/dts/nvidia/tegra194-p2888.dtsi |    2 +-
 .../boot/dts/nvidia/tegra194-p2972-0000.dts   |   41 +
 arch/arm64/boot/dts/nvidia/tegra194.dtsi      |  437 +++++
 arch/arm64/configs/defconfig                  |    1 +
 drivers/pci/controller/dwc/Kconfig            |   10 +
 drivers/pci/controller/dwc/Makefile           |    1 +
 .../pci/controller/dwc/pcie-designware-ep.c   |   37 +-
 .../pci/controller/dwc/pcie-designware-host.c |   14 +-
 drivers/pci/controller/dwc/pcie-designware.c  |   87 +
 drivers/pci/controller/dwc/pcie-designware.h  |   12 +
 drivers/pci/controller/dwc/pcie-tegra194.c    | 1621 +++++++++++++++++
 drivers/pci/quirks.c                          |   23 +
 drivers/phy/tegra/Kconfig                     |    7 +
 drivers/phy/tegra/Makefile                    |    1 +
 drivers/phy/tegra/phy-tegra194-p2u.c          |  109 ++
 include/uapi/linux/pci_regs.h                 |   22 +-
 20 files changed, 2575 insertions(+), 43 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
 create mode 100644 Documentation/devicetree/bindings/phy/phy-tegra194-p2u.txt
 create mode 100644 drivers/pci/controller/dwc/pcie-tegra194.c
 create mode 100644 drivers/phy/tegra/phy-tegra194-p2u.c

Comments

Thierry Reding June 6, 2019, 3:32 p.m. UTC | #1
On Sun, May 26, 2019 at 10:07:41AM +0530, Vidya Sagar wrote:
> Add extended configuration space capability search API using struct dw_pcie *
> pointer
> 
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
> ---
> Changes since [v7]:
> * Changed data types of return and arguments to be inline with data being returned
>   and passed.
> 
> Changes since [v6]:
> * None
> 
> Changes since [v5]:
> * None
> 
> Changes since [v4]:
> * None
> 
> Changes since [v3]:
> * None
> 
> Changes since [v2]:
> * None
> 
> Changes since [v1]:
> * This is a new patch in v2 series
> 
>  drivers/pci/controller/dwc/pcie-designware.c | 41 ++++++++++++++++++++
>  drivers/pci/controller/dwc/pcie-designware.h |  1 +
>  2 files changed, 42 insertions(+)

Acked-by: Thierry Reding <treding@nvidia.com>
Thierry Reding June 6, 2019, 3:36 p.m. UTC | #2
On Sun, May 26, 2019 at 10:07:50AM +0530, Vidya Sagar wrote:
> Add support for Synopsys DesignWare core IP based PCIe host controller
> present in Tegra194 SoC.
> 
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> ---
> Changes since [v7]:
> * Addressed review comments from Thierry
> 
> Changes since [v6]:
> * Removed code around "nvidia,disable-aspm-states" DT property
> * Refactored code to remove code duplication
> 
> Changes since [v5]:
> * Addressed review comments from Thierry
> 
> Changes since [v4]:
> * None
> 
> Changes since [v3]:
> * None
> 
> Changes since [v2]:
> * Changed 'nvidia,init-speed' to 'nvidia,init-link-speed'
> * Changed 'nvidia,pex-wake' to 'nvidia,wake-gpios'
> * Removed .runtime_suspend() & .runtime_resume() implementations
> 
> Changes since [v1]:
> * Made CONFIG_PCIE_TEGRA194 as 'm' by default from its previous 'y' state
> * Modified code as per changes made to DT documentation
> * Refactored code to address Bjorn & Thierry's review comments
> * Added goto to avoid recursion in tegra_pcie_dw_host_init() API
> * Merged .scan_bus() of dw_pcie_host_ops implementation to tegra_pcie_dw_host_init() API
> 
>  drivers/pci/controller/dwc/Kconfig         |   10 +
>  drivers/pci/controller/dwc/Makefile        |    1 +
>  drivers/pci/controller/dwc/pcie-tegra194.c | 1621 ++++++++++++++++++++
>  3 files changed, 1632 insertions(+)
>  create mode 100644 drivers/pci/controller/dwc/pcie-tegra194.c

Acked-by: Thierry Reding <treding@nvidia.com>
Dmitry Osipenko June 6, 2019, 4:30 p.m. UTC | #3
26.05.2019 7:37, Vidya Sagar пишет:
> Synopsys DesignWare core based PCIe controllers in Tegra 194 SoC interface
> with Universal PHY (UPHY) module through a PIPE2UPHY (P2U) module.
> For each PCIe lane of a controller, there is a P2U unit instantiated at
> hardware level. This driver provides support for the programming required
> for each P2U that is going to be used for a PCIe controller.
> 
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> ---
> Changes since [v7]:
> * Changed P2U driver file name from pcie-p2u-tegra194.c to phy-tegra194-p2u.c
> 
> Changes since [v6]:
> * None
> 
> Changes since [v5]:
> * Addressed review comments from Thierry
> 
> Changes since [v4]:
> * None
> 
> Changes since [v3]:
> * Rebased on top of linux-next top of the tree
> 
> Changes since [v2]:
> * Replaced spaces with tabs in Kconfig file
> * Sorted header file inclusion alphabetically
> 
> Changes since [v1]:
> * Added COMPILE_TEST in Kconfig
> * Removed empty phy_ops implementations
> * Modified code according to DT documentation file modifications
> 
>  drivers/phy/tegra/Kconfig            |   7 ++
>  drivers/phy/tegra/Makefile           |   1 +
>  drivers/phy/tegra/phy-tegra194-p2u.c | 109 +++++++++++++++++++++++++++
>  3 files changed, 117 insertions(+)
>  create mode 100644 drivers/phy/tegra/phy-tegra194-p2u.c
> 
> diff --git a/drivers/phy/tegra/Kconfig b/drivers/phy/tegra/Kconfig
> index a3b1de953fb7..c56fc8452e03 100644
> --- a/drivers/phy/tegra/Kconfig
> +++ b/drivers/phy/tegra/Kconfig
> @@ -6,3 +6,10 @@ config PHY_TEGRA_XUSB
>  
>  	  To compile this driver as a module, choose M here: the module will
>  	  be called phy-tegra-xusb.
> +
> +config PHY_TEGRA194_P2U
> +	tristate "NVIDIA Tegra194 PIPE2UPHY PHY driver"
> +	depends on ARCH_TEGRA || COMPILE_TEST

ARCH_TEGRA is a bit too much, ARCH_TEGRA_194_SOC should fit better here.
Dmitry Osipenko June 6, 2019, 4:35 p.m. UTC | #4
26.05.2019 7:37, Vidya Sagar пишет:
> Add support for Synopsys DesignWare core IP based PCIe host controller
> present in Tegra194 SoC.
> 
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> ---
> Changes since [v7]:
> * Addressed review comments from Thierry
> 
> Changes since [v6]:
> * Removed code around "nvidia,disable-aspm-states" DT property
> * Refactored code to remove code duplication
> 
> Changes since [v5]:
> * Addressed review comments from Thierry
> 
> Changes since [v4]:
> * None
> 
> Changes since [v3]:
> * None
> 
> Changes since [v2]:
> * Changed 'nvidia,init-speed' to 'nvidia,init-link-speed'
> * Changed 'nvidia,pex-wake' to 'nvidia,wake-gpios'
> * Removed .runtime_suspend() & .runtime_resume() implementations
> 
> Changes since [v1]:
> * Made CONFIG_PCIE_TEGRA194 as 'm' by default from its previous 'y' state
> * Modified code as per changes made to DT documentation
> * Refactored code to address Bjorn & Thierry's review comments
> * Added goto to avoid recursion in tegra_pcie_dw_host_init() API
> * Merged .scan_bus() of dw_pcie_host_ops implementation to tegra_pcie_dw_host_init() API
> 
>  drivers/pci/controller/dwc/Kconfig         |   10 +
>  drivers/pci/controller/dwc/Makefile        |    1 +
>  drivers/pci/controller/dwc/pcie-tegra194.c | 1621 ++++++++++++++++++++
>  3 files changed, 1632 insertions(+)
>  create mode 100644 drivers/pci/controller/dwc/pcie-tegra194.c
> 
> diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
> index a6ce1ee51b4c..884112afc11b 100644
> --- a/drivers/pci/controller/dwc/Kconfig
> +++ b/drivers/pci/controller/dwc/Kconfig
> @@ -220,6 +220,16 @@ config PCI_MESON
>  	  and therefore the driver re-uses the DesignWare core functions to
>  	  implement the driver.
>  
> +config PCIE_TEGRA194
> +	tristate "NVIDIA Tegra194 (and later) PCIe controller"
> +	depends on (TEGRA_BPMP && ARCH_TEGRA) || COMPILE_TEST

TEGRA_BPMP will be enough here as it depends on other relevant options.

Hence I mean:

	depends on TEGRA_BPMP || COMPILE_TEST


> +	depends on PCI_MSI_IRQ_DOMAIN

You probably want to s/depends on/select/ PCI_MSI_IRQ_DOMAIN, don't you?
Dmitry Osipenko June 6, 2019, 6:52 p.m. UTC | #5
06.06.2019 19:35, Dmitry Osipenko пишет:
> 26.05.2019 7:37, Vidya Sagar пишет:
>> Add support for Synopsys DesignWare core IP based PCIe host controller
>> present in Tegra194 SoC.
>>
>> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
>> ---
>> Changes since [v7]:
>> * Addressed review comments from Thierry
>>
>> Changes since [v6]:
>> * Removed code around "nvidia,disable-aspm-states" DT property
>> * Refactored code to remove code duplication
>>
>> Changes since [v5]:
>> * Addressed review comments from Thierry
>>
>> Changes since [v4]:
>> * None
>>
>> Changes since [v3]:
>> * None
>>
>> Changes since [v2]:
>> * Changed 'nvidia,init-speed' to 'nvidia,init-link-speed'
>> * Changed 'nvidia,pex-wake' to 'nvidia,wake-gpios'
>> * Removed .runtime_suspend() & .runtime_resume() implementations
>>
>> Changes since [v1]:
>> * Made CONFIG_PCIE_TEGRA194 as 'm' by default from its previous 'y' state
>> * Modified code as per changes made to DT documentation
>> * Refactored code to address Bjorn & Thierry's review comments
>> * Added goto to avoid recursion in tegra_pcie_dw_host_init() API
>> * Merged .scan_bus() of dw_pcie_host_ops implementation to tegra_pcie_dw_host_init() API
>>
>>  drivers/pci/controller/dwc/Kconfig         |   10 +
>>  drivers/pci/controller/dwc/Makefile        |    1 +
>>  drivers/pci/controller/dwc/pcie-tegra194.c | 1621 ++++++++++++++++++++
>>  3 files changed, 1632 insertions(+)
>>  create mode 100644 drivers/pci/controller/dwc/pcie-tegra194.c
>>
>> diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
>> index a6ce1ee51b4c..884112afc11b 100644
>> --- a/drivers/pci/controller/dwc/Kconfig
>> +++ b/drivers/pci/controller/dwc/Kconfig
>> @@ -220,6 +220,16 @@ config PCI_MESON
>>  	  and therefore the driver re-uses the DesignWare core functions to
>>  	  implement the driver.
>>  
>> +config PCIE_TEGRA194
>> +	tristate "NVIDIA Tegra194 (and later) PCIe controller"
>> +	depends on (TEGRA_BPMP && ARCH_TEGRA) || COMPILE_TEST
> 
> TEGRA_BPMP will be enough here as it depends on other relevant options.
> 
> Hence I mean:
> 
> 	depends on TEGRA_BPMP || COMPILE_TEST

Maybe it's worth to even change TEGRA_BPMP to ARCH_TEGRA_194_SOC.
Although then you'll have to extend it with other platforms later on,
but probably that's fine.

> 
>> +	depends on PCI_MSI_IRQ_DOMAIN
> 
> You probably want to s/depends on/select/ PCI_MSI_IRQ_DOMAIN, don't you?
> 

I actually looked up the PCI_MSI_IRQ_DOMAIN and it is correct in your
case, my bad.
Vidya Sagar June 7, 2019, 1:45 p.m. UTC | #6
On 6/6/2019 10:00 PM, Dmitry Osipenko wrote:
> 26.05.2019 7:37, Vidya Sagar пишет:
>> Synopsys DesignWare core based PCIe controllers in Tegra 194 SoC interface
>> with Universal PHY (UPHY) module through a PIPE2UPHY (P2U) module.
>> For each PCIe lane of a controller, there is a P2U unit instantiated at
>> hardware level. This driver provides support for the programming required
>> for each P2U that is going to be used for a PCIe controller.
>>
>> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
>> ---
>> Changes since [v7]:
>> * Changed P2U driver file name from pcie-p2u-tegra194.c to phy-tegra194-p2u.c
>>
>> Changes since [v6]:
>> * None
>>
>> Changes since [v5]:
>> * Addressed review comments from Thierry
>>
>> Changes since [v4]:
>> * None
>>
>> Changes since [v3]:
>> * Rebased on top of linux-next top of the tree
>>
>> Changes since [v2]:
>> * Replaced spaces with tabs in Kconfig file
>> * Sorted header file inclusion alphabetically
>>
>> Changes since [v1]:
>> * Added COMPILE_TEST in Kconfig
>> * Removed empty phy_ops implementations
>> * Modified code according to DT documentation file modifications
>>
>>   drivers/phy/tegra/Kconfig            |   7 ++
>>   drivers/phy/tegra/Makefile           |   1 +
>>   drivers/phy/tegra/phy-tegra194-p2u.c | 109 +++++++++++++++++++++++++++
>>   3 files changed, 117 insertions(+)
>>   create mode 100644 drivers/phy/tegra/phy-tegra194-p2u.c
>>
>> diff --git a/drivers/phy/tegra/Kconfig b/drivers/phy/tegra/Kconfig
>> index a3b1de953fb7..c56fc8452e03 100644
>> --- a/drivers/phy/tegra/Kconfig
>> +++ b/drivers/phy/tegra/Kconfig
>> @@ -6,3 +6,10 @@ config PHY_TEGRA_XUSB
>>   
>>   	  To compile this driver as a module, choose M here: the module will
>>   	  be called phy-tegra-xusb.
>> +
>> +config PHY_TEGRA194_P2U
>> +	tristate "NVIDIA Tegra194 PIPE2UPHY PHY driver"
>> +	depends on ARCH_TEGRA || COMPILE_TEST
> 
> ARCH_TEGRA is a bit too much, ARCH_TEGRA_194_SOC should fit better here.
> 
Ok. I'll take care of it in the next patch series.
Vidya Sagar June 7, 2019, 2:10 p.m. UTC | #7
On 6/7/2019 12:22 AM, Dmitry Osipenko wrote:
> 06.06.2019 19:35, Dmitry Osipenko пишет:
>> 26.05.2019 7:37, Vidya Sagar пишет:
>>> Add support for Synopsys DesignWare core IP based PCIe host controller
>>> present in Tegra194 SoC.
>>>
>>> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
>>> ---
>>> Changes since [v7]:
>>> * Addressed review comments from Thierry
>>>
>>> Changes since [v6]:
>>> * Removed code around "nvidia,disable-aspm-states" DT property
>>> * Refactored code to remove code duplication
>>>
>>> Changes since [v5]:
>>> * Addressed review comments from Thierry
>>>
>>> Changes since [v4]:
>>> * None
>>>
>>> Changes since [v3]:
>>> * None
>>>
>>> Changes since [v2]:
>>> * Changed 'nvidia,init-speed' to 'nvidia,init-link-speed'
>>> * Changed 'nvidia,pex-wake' to 'nvidia,wake-gpios'
>>> * Removed .runtime_suspend() & .runtime_resume() implementations
>>>
>>> Changes since [v1]:
>>> * Made CONFIG_PCIE_TEGRA194 as 'm' by default from its previous 'y' state
>>> * Modified code as per changes made to DT documentation
>>> * Refactored code to address Bjorn & Thierry's review comments
>>> * Added goto to avoid recursion in tegra_pcie_dw_host_init() API
>>> * Merged .scan_bus() of dw_pcie_host_ops implementation to tegra_pcie_dw_host_init() API
>>>
>>>   drivers/pci/controller/dwc/Kconfig         |   10 +
>>>   drivers/pci/controller/dwc/Makefile        |    1 +
>>>   drivers/pci/controller/dwc/pcie-tegra194.c | 1621 ++++++++++++++++++++
>>>   3 files changed, 1632 insertions(+)
>>>   create mode 100644 drivers/pci/controller/dwc/pcie-tegra194.c
>>>
>>> diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
>>> index a6ce1ee51b4c..884112afc11b 100644
>>> --- a/drivers/pci/controller/dwc/Kconfig
>>> +++ b/drivers/pci/controller/dwc/Kconfig
>>> @@ -220,6 +220,16 @@ config PCI_MESON
>>>   	  and therefore the driver re-uses the DesignWare core functions to
>>>   	  implement the driver.
>>>   
>>> +config PCIE_TEGRA194
>>> +	tristate "NVIDIA Tegra194 (and later) PCIe controller"
>>> +	depends on (TEGRA_BPMP && ARCH_TEGRA) || COMPILE_TEST
>>
>> TEGRA_BPMP will be enough here as it depends on other relevant options.
>>
>> Hence I mean:
>>
>> 	depends on TEGRA_BPMP || COMPILE_TEST
> 
> Maybe it's worth to even change TEGRA_BPMP to ARCH_TEGRA_194_SOC.
> Although then you'll have to extend it with other platforms later on,
> but probably that's fine.
I received an explicit comment previously to make this dependent on TEGRA_BPMP
as the driver is using APIs to get certain jobs done by BPMP-FW. But, since
we can't boot kernel in the first place without having BPMP-FW in place, I think
it should be fine to make it dependent on ARCH_TEGRA_194_SOC directly.

> 
>>
>>> +	depends on PCI_MSI_IRQ_DOMAIN
>>
>> You probably want to s/depends on/select/ PCI_MSI_IRQ_DOMAIN, don't you?
>>
> 
> I actually looked up the PCI_MSI_IRQ_DOMAIN and it is correct in your
> case, my bad.
>
Dmitry Osipenko June 7, 2019, 2:26 p.m. UTC | #8
07.06.2019 17:10, Vidya Sagar пишет:
> On 6/7/2019 12:22 AM, Dmitry Osipenko wrote:
>> 06.06.2019 19:35, Dmitry Osipenko пишет:
>>> 26.05.2019 7:37, Vidya Sagar пишет:
>>>> Add support for Synopsys DesignWare core IP based PCIe host controller
>>>> present in Tegra194 SoC.
>>>>
>>>> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
>>>> ---
>>>> Changes since [v7]:
>>>> * Addressed review comments from Thierry
>>>>
>>>> Changes since [v6]:
>>>> * Removed code around "nvidia,disable-aspm-states" DT property
>>>> * Refactored code to remove code duplication
>>>>
>>>> Changes since [v5]:
>>>> * Addressed review comments from Thierry
>>>>
>>>> Changes since [v4]:
>>>> * None
>>>>
>>>> Changes since [v3]:
>>>> * None
>>>>
>>>> Changes since [v2]:
>>>> * Changed 'nvidia,init-speed' to 'nvidia,init-link-speed'
>>>> * Changed 'nvidia,pex-wake' to 'nvidia,wake-gpios'
>>>> * Removed .runtime_suspend() & .runtime_resume() implementations
>>>>
>>>> Changes since [v1]:
>>>> * Made CONFIG_PCIE_TEGRA194 as 'm' by default from its previous 'y'
>>>> state
>>>> * Modified code as per changes made to DT documentation
>>>> * Refactored code to address Bjorn & Thierry's review comments
>>>> * Added goto to avoid recursion in tegra_pcie_dw_host_init() API
>>>> * Merged .scan_bus() of dw_pcie_host_ops implementation to
>>>> tegra_pcie_dw_host_init() API
>>>>
>>>>   drivers/pci/controller/dwc/Kconfig         |   10 +
>>>>   drivers/pci/controller/dwc/Makefile        |    1 +
>>>>   drivers/pci/controller/dwc/pcie-tegra194.c | 1621
>>>> ++++++++++++++++++++
>>>>   3 files changed, 1632 insertions(+)
>>>>   create mode 100644 drivers/pci/controller/dwc/pcie-tegra194.c
>>>>
>>>> diff --git a/drivers/pci/controller/dwc/Kconfig
>>>> b/drivers/pci/controller/dwc/Kconfig
>>>> index a6ce1ee51b4c..884112afc11b 100644
>>>> --- a/drivers/pci/controller/dwc/Kconfig
>>>> +++ b/drivers/pci/controller/dwc/Kconfig
>>>> @@ -220,6 +220,16 @@ config PCI_MESON
>>>>         and therefore the driver re-uses the DesignWare core
>>>> functions to
>>>>         implement the driver.
>>>>   +config PCIE_TEGRA194
>>>> +    tristate "NVIDIA Tegra194 (and later) PCIe controller"
>>>> +    depends on (TEGRA_BPMP && ARCH_TEGRA) || COMPILE_TEST
>>>
>>> TEGRA_BPMP will be enough here as it depends on other relevant options.
>>>
>>> Hence I mean:
>>>
>>>     depends on TEGRA_BPMP || COMPILE_TEST
>>
>> Maybe it's worth to even change TEGRA_BPMP to ARCH_TEGRA_194_SOC.
>> Although then you'll have to extend it with other platforms later on,
>> but probably that's fine.
> I received an explicit comment previously to make this dependent on
> TEGRA_BPMP
> as the driver is using APIs to get certain jobs done by BPMP-FW. But, since
> we can't boot kernel in the first place without having BPMP-FW in place,
> I think
> it should be fine to make it dependent on ARCH_TEGRA_194_SOC directly.

ARCH_TEGRA_194_SOC selects BPMP by itself (see
drivers/soc/tegra/Kconfig), so it's indeed absolutely fine.