Message ID | 64b9d81c.aefd.12f8c08e79a.Coremail.qemu_wanghuang@126.com |
---|---|
State | New |
Headers | show |
On Mon, Apr 25, 2011 at 05:41:24PM +0800, qemu_wanghuang wrote: > In Ful-system emulation, when we use "-d op_opt",we can not find the pc of guestinstruction in logfile.However,we can get this in log by using command "-d op". It is funny that when we use "-d op,op_opt",we get pc in both op's log and op_opt's log.It makes the command "-d op_opt" ambiguous. Please add a Signed-off-by: line to your patch. > wanghuang:ustc > ------------ > Index: target-cris/translate_v10.c > =================================================================== > --- target-cris/translate_v10.c (版本 2) > +++ target-cris/translate_v10.c (工作副本) > @@ -1150,7 +1150,8 @@ > > if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) > tcg_gen_debug_insn_start(dc->pc); > - > + else if(unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT))) > + tcg_gen_debug_insn_start(dc->pc); Instead of adding some more code doing the same, you should use something like: qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT) > /* Load a halfword onto the instruction register. */ > dc->ir = lduw_code(dc->pc); > > Index: target-cris/translate.c > =================================================================== > --- target-cris/translate.c (版本 2) > +++ target-cris/translate.c (工作副本) > @@ -3082,7 +3082,8 @@ > > if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) > tcg_gen_debug_insn_start(dc->pc); > - > + else if(unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT))) > + tcg_gen_debug_insn_start(dc->pc); > /* Load a halfword onto the instruction register. */ > dc->ir = cris_fetch(dc, dc->pc, 2, 0); > > Index: target-alpha/translate.c > =================================================================== > --- target-alpha/translate.c (版本 2) > +++ target-alpha/translate.c (工作副本) > @@ -3207,6 +3207,8 @@ > if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) { > tcg_gen_debug_insn_start(ctx.pc); > } > + else if(unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT))) > + tcg_gen_debug_insn_start(ctx.pc); > > ctx.pc += 4; > ret = translate_one(ctxp, insn); > Index: target-sparc/translate.c > =================================================================== > --- target-sparc/translate.c (版本 2) > +++ target-sparc/translate.c (工作副本) > @@ -1873,6 +1873,8 @@ > > if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) > tcg_gen_debug_insn_start(dc->pc); > + else if(unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT))) > + tcg_gen_debug_insn_start(dc->pc); > insn = ldl_code(dc->pc); > opc = GET_FIELD(insn, 0, 1); > > Index: target-ppc/translate.c > =================================================================== > --- target-ppc/translate.c (版本 2) > +++ target-ppc/translate.c (工作副本) > @@ -9036,6 +9036,8 @@ > opc3(ctx.opcode), little_endian ? "little" : "big"); > if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) > tcg_gen_debug_insn_start(ctx.nip); > + else if(unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT))) > + tcg_gen_debug_insn_start(ctx.nip); > ctx.nip += 4; > table = env->opcodes; > num_insns++; > Index: target-mips/translate.c > =================================================================== > --- target-mips/translate.c (版本 2) > +++ target-mips/translate.c (工作副本) > @@ -11631,7 +11631,8 @@ > > if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) > tcg_gen_debug_insn_start(ctx->pc); > - > + else if(unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT))) > + tcg_gen_debug_insn_start(ctx->pc); > op = MASK_OP_MAJOR(ctx->opcode); > rs = (ctx->opcode >> 21) & 0x1f; > rt = (ctx->opcode >> 16) & 0x1f; > Index: target-arm/translate.c > =================================================================== > --- target-arm/translate.c (版本 2) > +++ target-arm/translate.c (工作副本) > @@ -9204,6 +9204,8 @@ > if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) { > tcg_gen_debug_insn_start(dc->pc); > } > + else if(unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT))) > + tcg_gen_debug_insn_start(dc->pc); > > if (dc->thumb) { > disas_thumb_insn(env, dc); > Index: target-microblaze/translate.c > =================================================================== > --- target-microblaze/translate.c (版本 2) > +++ target-microblaze/translate.c (工作副本) > @@ -1510,7 +1510,8 @@ > > if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) > tcg_gen_debug_insn_start(dc->pc); > - > + else if(unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT))) > + tcg_gen_debug_insn_start(dc->pc); > dc->ir = ir = ldl_code(dc->pc); > LOG_DIS("%8.8x\t", dc->ir); > > Index: target-i386/translate.c > =================================================================== > --- target-i386/translate.c (版本 2) > +++ target-i386/translate.c (工作副本) > @@ -4070,6 +4070,8 @@ > > if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) > tcg_gen_debug_insn_start(pc_start); > + else if(unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT))) > + tcg_gen_debug_insn_start(pc_start); > s->pc = pc_start; > prefixes = 0; > aflag = s->code32; >
Am Montag 25 April 2011, 11:41:24 schrieb qemu_wanghuang: > In Ful-system emulation, when we use "-d op_opt",we can not find the pc of > guestinstruction in logfile.However,we can get this in log by using > command "-d op". It is funny that when we use "-d op,op_opt",we get pc in > both op's log and op_opt's log.It makes the command "-d op_opt" ambiguous. target-lm32 is missing in this patch.
Index: target-cris/translate_v10.c =================================================================== --- target-cris/translate_v10.c (版本 2) +++ target-cris/translate_v10.c (工作副本) @@ -1150,7 +1150,8 @@ if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) tcg_gen_debug_insn_start(dc->pc); - + else if(unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT))) + tcg_gen_debug_insn_start(dc->pc); /* Load a halfword onto the instruction register. */ dc->ir = lduw_code(dc->pc); Index: target-cris/translate.c =================================================================== --- target-cris/translate.c (版本 2) +++ target-cris/translate.c (工作副本) @@ -3082,7 +3082,8 @@ if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) tcg_gen_debug_insn_start(dc->pc); - + else if(unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT))) + tcg_gen_debug_insn_start(dc->pc); /* Load a halfword onto the instruction register. */ dc->ir = cris_fetch(dc, dc->pc, 2, 0); Index: target-alpha/translate.c =================================================================== --- target-alpha/translate.c (版本 2) +++ target-alpha/translate.c (工作副本) @@ -3207,6 +3207,8 @@ if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) { tcg_gen_debug_insn_start(ctx.pc); } + else if(unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT))) + tcg_gen_debug_insn_start(ctx.pc); ctx.pc += 4; ret = translate_one(ctxp, insn); Index: target-sparc/translate.c =================================================================== --- target-sparc/translate.c (版本 2) +++ target-sparc/translate.c (工作副本) @@ -1873,6 +1873,8 @@ if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) tcg_gen_debug_insn_start(dc->pc); + else if(unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT))) + tcg_gen_debug_insn_start(dc->pc); insn = ldl_code(dc->pc); opc = GET_FIELD(insn, 0, 1); Index: target-ppc/translate.c =================================================================== --- target-ppc/translate.c (版本 2) +++ target-ppc/translate.c (工作副本) @@ -9036,6 +9036,8 @@ opc3(ctx.opcode), little_endian ? "little" : "big"); if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) tcg_gen_debug_insn_start(ctx.nip); + else if(unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT))) + tcg_gen_debug_insn_start(ctx.nip); ctx.nip += 4; table = env->opcodes; num_insns++; Index: target-mips/translate.c =================================================================== --- target-mips/translate.c (版本 2) +++ target-mips/translate.c (工作副本) @@ -11631,7 +11631,8 @@ if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) tcg_gen_debug_insn_start(ctx->pc); - + else if(unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT))) + tcg_gen_debug_insn_start(ctx->pc); op = MASK_OP_MAJOR(ctx->opcode); rs = (ctx->opcode >> 21) & 0x1f; rt = (ctx->opcode >> 16) & 0x1f; Index: target-arm/translate.c =================================================================== --- target-arm/translate.c (版本 2) +++ target-arm/translate.c (工作副本) @@ -9204,6 +9204,8 @@ if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) { tcg_gen_debug_insn_start(dc->pc); } + else if(unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT))) + tcg_gen_debug_insn_start(dc->pc); if (dc->thumb) { disas_thumb_insn(env, dc); Index: target-microblaze/translate.c =================================================================== --- target-microblaze/translate.c (版本 2) +++ target-microblaze/translate.c (工作副本) @@ -1510,7 +1510,8 @@ if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) tcg_gen_debug_insn_start(dc->pc); - + else if(unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT))) + tcg_gen_debug_insn_start(dc->pc); dc->ir = ir = ldl_code(dc->pc); LOG_DIS("%8.8x\t", dc->ir); Index: target-i386/translate.c =================================================================== --- target-i386/translate.c (版本 2) +++ target-i386/translate.c (工作副本) @@ -4070,6 +4070,8 @@ if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) tcg_gen_debug_insn_start(pc_start); + else if(unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT))) + tcg_gen_debug_insn_start(pc_start); s->pc = pc_start; prefixes = 0; aflag = s->code32;