| Message ID | 20190305024401.2665-10-peng.fan@nxp.com |
|---|---|
| State | Awaiting Upstream |
| Delegated to: | Stefano Babic |
| Headers | show |
| Series | [U-Boot,RESEND,01/10] pinctrl: imx8: add i.MX8QM compatible | expand |
Hi Stefano, Fabio Any comments on this patchset? Thanks, Peng. > -----Original Message----- > From: Peng Fan [mailto:peng.fan@nxp.com] > Sent: 2019年3月5日 10:33 > To: sbabic@denx.de; Fabio Estevam <fabio.estevam@nxp.com> > Cc: u-boot@lists.denx.de; van.freenix@gmail.com; dl-uboot-imx > <uboot-imx@nxp.com>; Peng Fan <peng.fan@nxp.com> > Subject: [PATCH RESEND 10/10] imx: support i.MX8QM MEK board > > Add i.MX8QM MEK board support. > Included a basic dts, enabled SPL FIT > > Boot log as below: > U-Boot SPL 2019.01-rc1-00029-gf002213219 (Dec 24 2018 - 10:28:30 +0800) > Normal Boot Trying to boot from MMC2_2 > > U-Boot 2019.01-rc1-00029-gf002213219 (Dec 24 2018 - 10:28:30 +0800) > > CPU: NXP i.MX8QM RevB A53 at 142933 MHz > > Model: Freescale i.MX8QM MEK > Board: iMX8QM MEK > Build: SCFW 9330215b > Boot: SD1 > DRAM: 6 GiB > MMC: FSL_SDHC: 0, FSL_SDHC: 1 > Loading Environment from MMC... *** Warning - bad CRC, using default > environment > > In: serial@5a060000 > Out: serial@5a060000 > Err: serial@5a060000 > Net: > Error: ethernet@5b040000 address not set. > eth-1: ethernet@5b040000 > Hit any key to stop autoboot: 0 > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > --- > arch/arm/dts/Makefile | 4 +- > arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi | 112 +++++++++++++++++++ > arch/arm/dts/fsl-imx8qm-mek.dts | 184 > ++++++++++++++++++++++++++++++++ > arch/arm/mach-imx/imx8/Kconfig | 6 ++ > board/freescale/imx8qm_mek/Kconfig | 14 +++ > board/freescale/imx8qm_mek/MAINTAINERS | 6 ++ > board/freescale/imx8qm_mek/Makefile | 8 ++ > board/freescale/imx8qm_mek/README | 57 ++++++++++ > board/freescale/imx8qm_mek/imx8qm_mek.c | 157 > +++++++++++++++++++++++++++ > board/freescale/imx8qm_mek/imximage.cfg | 19 ++++ > board/freescale/imx8qm_mek/spl.c | 75 +++++++++++++ > configs/imx8qm_mek_defconfig | 75 +++++++++++++ > include/configs/imx8qm_mek.h | 176 > ++++++++++++++++++++++++++++++ > 13 files changed, 892 insertions(+), 1 deletion(-) create mode 100644 > arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi > create mode 100644 arch/arm/dts/fsl-imx8qm-mek.dts create mode > 100644 board/freescale/imx8qm_mek/Kconfig > create mode 100644 board/freescale/imx8qm_mek/MAINTAINERS > create mode 100644 board/freescale/imx8qm_mek/Makefile > create mode 100644 board/freescale/imx8qm_mek/README create mode > 100644 board/freescale/imx8qm_mek/imx8qm_mek.c > create mode 100644 board/freescale/imx8qm_mek/imximage.cfg > create mode 100644 board/freescale/imx8qm_mek/spl.c create mode > 100644 configs/imx8qm_mek_defconfig create mode 100644 > include/configs/imx8qm_mek.h > > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index > 2a040b20a5..954d595391 100644 > --- a/arch/arm/dts/Makefile > +++ b/arch/arm/dts/Makefile > @@ -486,7 +486,9 @@ dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \ > > dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb > > -dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qxp-mek.dtb > +dtb-$(CONFIG_ARCH_IMX8) += \ > + fsl-imx8qxp-mek.dtb \ > + fsl-imx8qm-mek.dtb \ > > dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb > > diff --git a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi > b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi > new file mode 100644 > index 0000000000..5d50eb028e > --- /dev/null > +++ b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi > @@ -0,0 +1,112 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright 2018 NXP > + */ > + > +&mu { > + u-boot,dm-spl; > +}; > + > +&clk { > + u-boot,dm-spl; > +}; > + > +&iomuxc { > + u-boot,dm-spl; > +}; > + > +&pd_lsio { > + u-boot,dm-spl; > +}; > + > +&pd_lsio_gpio0 { > + u-boot,dm-spl; > +}; > + > +&pd_lsio_gpio1 { > + u-boot,dm-spl; > +}; > + > +&pd_lsio_gpio2 { > + u-boot,dm-spl; > +}; > + > +&pd_lsio_gpio3 { > + u-boot,dm-spl; > +}; > + > +&pd_lsio_gpio4 { > + u-boot,dm-spl; > +}; > + > +&pd_lsio_gpio5 { > + u-boot,dm-spl; > +}; > + > +&pd_lsio_gpio6 { > + u-boot,dm-spl; > +}; > + > +&pd_lsio_gpio7 { > + u-boot,dm-spl; > +}; > + > +&pd_conn { > + u-boot,dm-spl; > +}; > + > +&pd_conn_sdch0 { > + u-boot,dm-spl; > +}; > + > +&pd_conn_sdch1 { > + u-boot,dm-spl; > +}; > + > +&pd_conn_sdch2 { > + u-boot,dm-spl; > +}; > + > +&gpio0 { > + u-boot,dm-spl; > +}; > + > +&gpio1 { > + u-boot,dm-spl; > +}; > + > +&gpio2 { > + u-boot,dm-spl; > +}; > + > +&gpio3 { > + u-boot,dm-spl; > +}; > + > +&gpio4 { > + u-boot,dm-spl; > +}; > + > +&gpio5 { > + u-boot,dm-spl; > +}; > + > +&gpio6 { > + u-boot,dm-spl; > +}; > + > +&gpio7 { > + u-boot,dm-spl; > +}; > + > +&lpuart0 { > + u-boot,dm-spl; > +}; > + > +&usdhc1 { > + u-boot,dm-spl; > +}; > + > +&usdhc2 { > + u-boot,dm-spl; > +}; > diff --git a/arch/arm/dts/fsl-imx8qm-mek.dts > b/arch/arm/dts/fsl-imx8qm-mek.dts new file mode 100644 index > 0000000000..63908ba6bf > --- /dev/null > +++ b/arch/arm/dts/fsl-imx8qm-mek.dts > @@ -0,0 +1,184 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright 2017-2018 NXP > + */ > + > +/dts-v1/; > + > +#include "fsl-imx8qm.dtsi" > +#include "fsl-imx8qm-mek-u-boot.dtsi" > + > +/ { > + model = "Freescale i.MX8QM MEK"; > + compatible = "fsl,imx8qm-mek", "fsl,imx8qm"; > + > + chosen { > + bootargs = "console=ttyLP0,115200 > earlycon=lpuart32,0x5a060000,115200"; > + stdout-path = &lpuart0; > + }; > + > + reg_usdhc2_vmmc: usdhc2_vmmc { > + compatible = "regulator-fixed"; > + regulator-name = "sw-3p3-sd1"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; > + off-on-delay = <4800>; > + enable-active-high; > + }; > +}; > + > +&iomuxc { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_hog>; > + > + imx8qm-mek { > + pinctrl_hog: hoggrp { > + fsl,pins = < > + SC_P_MCLK_OUT0_AUD_ACM_MCLK_OUT0 > 0x0600004c > + SC_P_QSPI1A_DATA1_LSIO_GPIO4_IO25 0x0600004c > + SC_P_SCU_GPIO0_03_LSIO_GPIO0_IO31 0x0600004c > + >; > + }; > + > + pinctrl_fec1: fec1grp { > + fsl,pins = < > + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD > 0x000014a0 > + SC_P_ENET0_MDC_CONN_ENET0_MDC > 0x06000020 > + SC_P_ENET0_MDIO_CONN_ENET0_MDIO > 0x06000020 > + > SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL > 0x00000061 > + SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC > 0x00000061 > + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 > 0x00000061 > + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 > 0x00000061 > + SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 > 0x00000061 > + SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 > 0x00000061 > + SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC > 0x00000061 > + > SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL > 0x00000061 > + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 > 0x00000061 > + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 > 0x00000061 > + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 > 0x00000061 > + SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 > 0x00000061 > + >; > + }; > + > + pinctrl_fec2: fec2grp { > + fsl,pins = < > + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD > 0x000014a0 > + > SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL > 0x00000060 > + SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC > 0x00000060 > + SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 > 0x00000060 > + SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 > 0x00000060 > + SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 > 0x00000060 > + SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 > 0x00000060 > + SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC > 0x00000060 > + > SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL > 0x00000060 > + SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 > 0x00000060 > + SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 > 0x00000060 > + SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 > 0x00000060 > + SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 > 0x00000060 > + >; > + }; > + > + pinctrl_lpuart0: lpuart0grp { > + fsl,pins = < > + SC_P_UART0_RX_DMA_UART0_RX 0x06000020 > + SC_P_UART0_TX_DMA_UART0_TX 0x06000020 > + >; > + }; > + > + pinctrl_usdhc1: usdhc1grp { > + fsl,pins = < > + SC_P_EMMC0_CLK_CONN_EMMC0_CLK > 0x06000041 > + SC_P_EMMC0_CMD_CONN_EMMC0_CMD > 0x00000021 > + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 > 0x00000021 > + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 > 0x00000021 > + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 > 0x00000021 > + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 > 0x00000021 > + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 > 0x00000021 > + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 > 0x00000021 > + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 > 0x00000021 > + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 > 0x00000021 > + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE > 0x00000041 > + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B > 0x00000021 > + >; > + }; > + > + pinctrl_usdhc2_gpio: usdhc2grpgpio { > + fsl,pins = < > + SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021 > + SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021 > + SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07 > 0x00000021 > + >; > + }; > + > + pinctrl_usdhc2: usdhc2grp { > + fsl,pins = < > + SC_P_USDHC1_CLK_CONN_USDHC1_CLK > 0x06000041 > + SC_P_USDHC1_CMD_CONN_USDHC1_CMD > 0x00000021 > + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 > 0x00000021 > + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 > 0x00000021 > + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 > 0x00000021 > + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 > 0x00000021 > + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT > 0x00000021 > + >; > + }; > + }; > +}; > + > +&usdhc1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_usdhc1>; > + bus-width = <8>; > + non-removable; > + status = "okay"; > +}; > + > +&usdhc2 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; > + bus-width = <4>; > + cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; > + wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; > + vmmc-supply = <®_usdhc2_vmmc>; > + status = "okay"; > +}; > + > +&fec1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_fec1>; > + phy-mode = "rgmii-txid"; > + phy-handle = <ðphy0>; > + fsl,magic-packet; > + fsl,rgmii_rxc_dly; > + status = "okay"; > + > + mdio { > + #address-cells = <1>; > + #size-cells = <0>; > + > + ethphy0: ethernet-phy@0 { > + compatible = "ethernet-phy-ieee802.3-c22"; > + reg = <0>; > + at803x,eee-disabled; > + at803x,vddio-1p8v; > + }; > + > + ethphy1: ethernet-phy@1 { > + compatible = "ethernet-phy-ieee802.3-c22"; > + reg = <1>; > + at803x,eee-disabled; > + at803x,vddio-1p8v; > + status = "disabled"; > + }; > + }; > +}; > + > +&lpuart0 { /* console */ > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_lpuart0>; > + status = "okay"; > +}; > + > +&gpio1 { > + status = "okay"; > +}; > diff --git a/arch/arm/mach-imx/imx8/Kconfig > b/arch/arm/mach-imx/imx8/Kconfig index 4336a8c236..c32f7dbb61 100644 > --- a/arch/arm/mach-imx/imx8/Kconfig > +++ b/arch/arm/mach-imx/imx8/Kconfig > @@ -32,8 +32,14 @@ config TARGET_IMX8QXP_MEK > select BOARD_LATE_INIT > select IMX8QXP > > +config TARGET_IMX8QM_MEK > + bool "Support i.MX8QM MEK board" > + select BOARD_LATE_INIT > + select IMX8QM > + > endchoice > > source "board/freescale/imx8qxp_mek/Kconfig" > +source "board/freescale/imx8qm_mek/Kconfig" > > endif > diff --git a/board/freescale/imx8qm_mek/Kconfig > b/board/freescale/imx8qm_mek/Kconfig > new file mode 100644 > index 0000000000..93d7d5f9c5 > --- /dev/null > +++ b/board/freescale/imx8qm_mek/Kconfig > @@ -0,0 +1,14 @@ > +if TARGET_IMX8QM_MEK > + > +config SYS_BOARD > + default "imx8qm_mek" > + > +config SYS_VENDOR > + default "freescale" > + > +config SYS_CONFIG_NAME > + default "imx8qm_mek" > + > +source "board/freescale/common/Kconfig" > + > +endif > diff --git a/board/freescale/imx8qm_mek/MAINTAINERS > b/board/freescale/imx8qm_mek/MAINTAINERS > new file mode 100644 > index 0000000000..115830df19 > --- /dev/null > +++ b/board/freescale/imx8qm_mek/MAINTAINERS > @@ -0,0 +1,6 @@ > +i.MX8QM MEK BOARD > +M: Peng Fan <peng.fan@nxp.com> > +S: Maintained > +F: board/freescale/imx8qm_mek/ > +F: include/configs/imx8qm_mek.h > +F: configs/imx8qm_mek_defconfig > diff --git a/board/freescale/imx8qm_mek/Makefile > b/board/freescale/imx8qm_mek/Makefile > new file mode 100644 > index 0000000000..bc9a1260bd > --- /dev/null > +++ b/board/freescale/imx8qm_mek/Makefile > @@ -0,0 +1,8 @@ > +# > +# Copyright 2018 NXP > +# > +# SPDX-License-Identifier: GPL-2.0+ > +# > + > +obj-y += imx8qm_mek.o > +obj-$(CONFIG_SPL_BUILD) += spl.o > diff --git a/board/freescale/imx8qm_mek/README > b/board/freescale/imx8qm_mek/README > new file mode 100644 > index 0000000000..c3523801ae > --- /dev/null > +++ b/board/freescale/imx8qm_mek/README > @@ -0,0 +1,57 @@ > +U-Boot for the NXP i.MX8QM EVK board > + > +Quick Start > +=========== > + > +- Build the ARM Trusted firmware binary > +- Get scfw_tcm.bin and ahab-container.img > +- Build U-Boot > +- Flash the binary into the SD card > +- Boot > + > +Get and Build the ARM Trusted firmware > +====================================== > + > +$ git clone https://source.codeaurora.org/external/imx/imx-atf > +$ cd imx-atf/ > +$ git checkout origin/imx_4.14.78_1.0.0_ga -b imx_4.14.78_1.0.0_ga $ > +make PLAT=imx8qm bl31 > + > +Get scfw_tcm.bin and ahab-container.img > ============================== > + > +$ wget > +https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-sc-firmware-1.1.bin > +$ chmod +x imx-sc-firmware-1.1.bin > +$ ./imx-sc-firmware-1.1.bin > +$ wget > https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin > +$ chmod +x firmware-imx-8.0.bin > +$ ./firmware-imx-8.0.bin > + > +Copy the following binaries to U-Boot folder: > + > +$ cp imx-atf/build/imx8qm/release/bl31.bin . > +$ cp u-boot/u-boot.bin . > + > +Copy the following firmwares U-Boot folder : > + > +$ cp firmware-imx-7.6/firmware/seco/ahab-container.img . > +$ cp imx-sc-firmware-0.7/mx8qm-mek-scfw-tcm.bin . > + > +Build U-Boot > +============ > +$ export ATF_LOAD_ADDR=0x80000000 > +$ export BL33_LOAD_ADDR=0x80020000 > +$ make imx8qm_mek_defconfig > +$ make flash.bin > +$ dd if=u-boot.itb of=flash.bin bs=512 seek=1984 > + > +Flash the binary into the SD card > +================================= > + > +Burn the flash.bin binary to SD card offset 32KB: > + > +$ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32 > + > +Boot > +==== > +Set Boot switch SW2: 1100. > diff --git a/board/freescale/imx8qm_mek/imx8qm_mek.c > b/board/freescale/imx8qm_mek/imx8qm_mek.c > new file mode 100644 > index 0000000000..e69efc4dd6 > --- /dev/null > +++ b/board/freescale/imx8qm_mek/imx8qm_mek.c > @@ -0,0 +1,157 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright 2018 NXP > + */ > + > +#include <common.h> > +#include <errno.h> > +#include <linux/libfdt.h> > +#include <environment.h> > +#include <asm/io.h> > +#include <asm/gpio.h> > +#include <asm/arch/clock.h> > +#include <asm/arch/sci/sci.h> > +#include <asm/arch/imx8-pins.h> > +#include <asm/arch/iomux.h> > +#include <asm/arch/sys_proto.h> > + > +DECLARE_GLOBAL_DATA_PTR; > + > +#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << > PADRING_CONFIG_SHIFT) | \ > + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ > + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | > \ > + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) > + > +static iomux_cfg_t uart0_pads[] = { > + SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL), > + SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL), }; > + > +static void setup_iomux_uart(void) > +{ > + imx8_iomux_setup_multiple_pads(uart0_pads, > ARRAY_SIZE(uart0_pads)); } > + > +int board_early_init_f(void) > +{ > + int ret; > + /* Set UART0 clock root to 80 MHz */ > + sc_pm_clock_rate_t rate = 80000000; > + > + /* Power up UART0 */ > + ret = sc_pm_set_resource_power_mode(-1, SC_R_UART_0, > SC_PM_PW_MODE_ON); > + if (ret) > + return ret; > + > + ret = sc_pm_set_clock_rate(-1, SC_R_UART_0, 2, &rate); > + if (ret) > + return ret; > + > + /* Enable UART0 clock root */ > + ret = sc_pm_clock_enable(-1, SC_R_UART_0, 2, true, false); > + if (ret) > + return ret; > + > + setup_iomux_uart(); > + > + sc_pm_set_resource_power_mode(-1, SC_R_GPIO_5, > SC_PM_PW_MODE_ON); > + > + return 0; > +} > + > +#if IS_ENABLED(CONFIG_DM_GPIO) > +static void board_gpio_init(void) > +{ > + /* TODO */ > +} > +#else > +static inline void board_gpio_init(void) {} #endif > + > +#if IS_ENABLED(CONFIG_FEC_MXC) > +#include <miiphy.h> > + > +int board_phy_config(struct phy_device *phydev) { > + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); > + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); > + > + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00); > + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee); > + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); > + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); > + > + if (phydev->drv->config) > + phydev->drv->config(phydev); > + > + return 0; > +} > +#endif > + > +void build_info(void) > +{ > + u32 sc_build = 0, sc_commit = 0; > + > + /* Get SCFW build and commit id */ > + sc_misc_build_info(-1, &sc_build, &sc_commit); > + if (!sc_build) { > + printf("SCFW does not support build info\n"); > + sc_commit = 0; /* Display 0 when the build info is not supported*/ > + } > + printf("Build: SCFW %x\n", sc_commit); } > + > +int checkboard(void) > +{ > + puts("Board: iMX8QM MEK\n"); > + > + build_info(); > + print_bootinfo(); > + > + return 0; > +} > + > +int board_init(void) > +{ > + /* Power up base board */ > + sc_pm_set_resource_power_mode(-1, SC_R_BOARD_R1, > SC_PM_PW_MODE_ON); > + > + board_gpio_init(); > + > + return 0; > +} > + > +void detail_board_ddr_info(void) > +{ > + puts("\nDDR "); > +} > + > +/* > + * Board specific reset that is system reset. > + */ > +void reset_cpu(ulong addr) > +{ > + /* TODO */ > +} > + > +#ifdef CONFIG_OF_BOARD_SETUP > +int ft_board_setup(void *blob, bd_t *bd) { > + return 0; > +} > +#endif > + > +int board_mmc_get_env_dev(int devno) > +{ > + return devno; > +} > + > +int board_late_init(void) > +{ > +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG > + env_set("board_name", "MEK"); > + env_set("board_rev", "iMX8QM"); > +#endif > + > + return 0; > +} > diff --git a/board/freescale/imx8qm_mek/imximage.cfg > b/board/freescale/imx8qm_mek/imximage.cfg > new file mode 100644 > index 0000000000..7dc6b93eb5 > --- /dev/null > +++ b/board/freescale/imx8qm_mek/imximage.cfg > @@ -0,0 +1,19 @@ > +/* SPDX-License-Identifier: GPL-2.0+ */ > +/* > + * Copyright 2018 NXP > + */ > + > +#define __ASSEMBLY__ > + > +/* Boot from SD, sector size 0x400 */ > +BOOT_FROM SD 0x400 > +/* SoC type IMX8QM */ > +SOC_TYPE IMX8QM > +/* Append seco container image */ > +APPEND mx8qm-ahab-container.img > +/* Create the 2nd container */ > +CONTAINER > +/* Add scfw image with exec attribute */ IMAGE SCU > +mx8qm-mek-scfw-tcm.bin > +/* Add ATF image with exec attribute */ IMAGE A35 spl/u-boot-spl.bin > +0x00100000 > diff --git a/board/freescale/imx8qm_mek/spl.c > b/board/freescale/imx8qm_mek/spl.c > new file mode 100644 > index 0000000000..95ce9f37e8 > --- /dev/null > +++ b/board/freescale/imx8qm_mek/spl.c > @@ -0,0 +1,75 @@ > +/* > + * Copyright 2018 NXP > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#include <common.h> > +#include <dm.h> > +#include <spl.h> > +#include <dm/uclass.h> > +#include <dm/device.h> > +#include <dm/uclass-internal.h> > +#include <dm/device-internal.h> > +#include <dm/lists.h> > + > +DECLARE_GLOBAL_DATA_PTR; > + > +void spl_board_init(void) > +{ > + struct udevice *dev; > + int offset; > + > + uclass_find_first_device(UCLASS_MISC, &dev); > + > + for (; dev; uclass_find_next_device(&dev)) { > + if (device_probe(dev)) > + continue; > + } > + > + offset = fdt_node_offset_by_compatible(gd->fdt_blob, -1, > "nxp,imx8-pd"); > + while (offset != -FDT_ERR_NOTFOUND) { > + lists_bind_fdt(gd->dm_root, offset_to_ofnode(offset), > + NULL, true); > + offset = fdt_node_offset_by_compatible(gd->fdt_blob, offset, > + "nxp,imx8-pd"); > + } > + > + uclass_find_first_device(UCLASS_POWER_DOMAIN, &dev); > + > + for (; dev; uclass_find_next_device(&dev)) { > + if (device_probe(dev)) > + continue; > + } > + > + arch_cpu_init(); > + > + board_early_init_f(); > + > + timer_init(); > + > + preloader_console_init(); > + > + puts("Normal Boot\n"); > +} > + > +#ifdef CONFIG_SPL_LOAD_FIT > +int board_fit_config_name_match(const char *name) { > + /* Just empty function now - can't decide what to choose */ > + debug("%s: %s\n", __func__, name); > + > + return 0; > +} > +#endif > + > +void board_init_f(ulong dummy) > +{ > + /* Clear global data */ > + memset((void *)gd, 0, sizeof(gd_t)); > + > + /* Clear the BSS. */ > + memset(__bss_start, 0, __bss_end - __bss_start); > + > + board_init_r(NULL, 0); > +} > diff --git a/configs/imx8qm_mek_defconfig b/configs/imx8qm_mek_defconfig > new file mode 100644 index 0000000000..238d44d1f5 > --- /dev/null > +++ b/configs/imx8qm_mek_defconfig > @@ -0,0 +1,75 @@ > +CONFIG_ARM=y > +CONFIG_ARCH_IMX8=y > +CONFIG_SYS_TEXT_BASE=0x80020000 > +CONFIG_SPL_GPIO_SUPPORT=y > +CONFIG_SPL_LIBCOMMON_SUPPORT=y > +CONFIG_SPL_LIBGENERIC_SUPPORT=y > +CONFIG_SYS_MALLOC_F_LEN=0x2000 > +CONFIG_TARGET_IMX8QM_MEK=y > +CONFIG_SPL_MMC_SUPPORT=y > +CONFIG_SPL_SERIAL_SUPPORT=y > +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y > +CONFIG_SPL=y > +CONFIG_NR_DRAM_BANKS=3 > +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" > +CONFIG_FIT=y > +CONFIG_SPL_LOAD_FIT=y > +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qm_m > ek/imximage.cfg" > +CONFIG_BOOTDELAY=3 > +CONFIG_LOG=y > +CONFIG_SPL_BOARD_INIT=y > +CONFIG_SPL_SEPARATE_BSS=y > +CONFIG_SPL_POWER_SUPPORT=y > +CONFIG_SPL_POWER_DOMAIN=y > +CONFIG_SPL_WATCHDOG_SUPPORT=y > +CONFIG_CMD_CPU=y > +# CONFIG_CMD_IMPORTENV is not set > +CONFIG_CMD_CLK=y > +CONFIG_CMD_DM=y > +CONFIG_CMD_GPIO=y > +CONFIG_CMD_I2C=y > +CONFIG_CMD_MMC=y > +CONFIG_CMD_DHCP=y > +CONFIG_CMD_MII=y > +CONFIG_CMD_PING=y > +CONFIG_CMD_CACHE=y > +CONFIG_CMD_FAT=y > +CONFIG_SPL_OF_CONTROL=y > +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek" > +CONFIG_ENV_IS_IN_MMC=y > +CONFIG_SPL_DM=y > +CONFIG_SPL_CLK=y > +CONFIG_CLK_IMX8=y > +CONFIG_CPU=y > +CONFIG_DM_GPIO=y > +CONFIG_MXC_GPIO=y > +CONFIG_DM_PCA953X=y > +CONFIG_DM_I2C=y > +CONFIG_SYS_I2C_IMX_LPI2C=y > +CONFIG_I2C_MUX=y > +CONFIG_I2C_MUX_PCA954x=y > +CONFIG_MISC=y > +CONFIG_DM_MMC=y > +CONFIG_PHYLIB=y > +CONFIG_PHY_ADDR_ENABLE=y > +CONFIG_PHY_ATHEROS=y > +CONFIG_DM_ETH=y > +CONFIG_PHY_GIGE=y > +CONFIG_FEC_MXC_SHARE_MDIO=y > +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 > +CONFIG_FEC_MXC=y > +CONFIG_MII=y > +CONFIG_PINCTRL=y > +CONFIG_SPL_PINCTRL=y > +CONFIG_PINCTRL_IMX8=y > +CONFIG_POWER_DOMAIN=y > +CONFIG_IMX8_POWER_DOMAIN=y > +CONFIG_DM_REGULATOR=y > +CONFIG_SPL_DM_REGULATOR=y > +CONFIG_DM_REGULATOR_FIXED=y > +CONFIG_DM_REGULATOR_GPIO=y > +CONFIG_SPL_DM_REGULATOR_GPIO=y > +CONFIG_DM_SERIAL=y > +CONFIG_FSL_LPUART=y > +CONFIG_SPL_TINY_MEMSET=y > +# CONFIG_EFI_LOADER is not set > diff --git a/include/configs/imx8qm_mek.h b/include/configs/imx8qm_mek.h > new file mode 100644 index 0000000000..02c5d1c054 > --- /dev/null > +++ b/include/configs/imx8qm_mek.h > @@ -0,0 +1,176 @@ > +/* SPDX-License-Identifier: GPL-2.0+ */ > +/* > + * Copyright 2018 NXP > + */ > + > +#ifndef __IMX8QM_MEK_H > +#define __IMX8QM_MEK_H > + > +#include <linux/sizes.h> > +#include <asm/arch/imx-regs.h> > + > +#ifdef CONFIG_SPL_BUILD > +#define CONFIG_SPL_TEXT_BASE 0x0 > +#define CONFIG_SPL_MAX_SIZE (124 * 1024) > +#define CONFIG_SYS_MONITOR_LEN (1024 * 1024) > +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR > +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR > 0x800 > +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 0 > + > +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" > +#define CONFIG_SPL_STACK 0x013E000 > +#define CONFIG_SPL_BSS_START_ADDR 0x00128000 > +#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */ > +#define CONFIG_SYS_SPL_MALLOC_START 0x00120000 > +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */ > +#define CONFIG_SERIAL_LPUART_BASE 0x5a060000 > +#define CONFIG_SYS_ICACHE_OFF > +#define CONFIG_SYS_DCACHE_OFF > +#define CONFIG_MALLOC_F_ADDR 0x00120000 > + > +#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE > + > +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE > + > +#define CONFIG_OF_EMBED > +#endif > + > +#define CONFIG_REMAKE_ELF > + > +#define CONFIG_BOARD_EARLY_INIT_F > + > +/* Flat Device Tree Definitions */ > +#define CONFIG_OF_BOARD_SETUP > + > +#undef CONFIG_CMD_EXPORTENV > +#undef CONFIG_CMD_IMPORTENV > +#undef CONFIG_CMD_IMLS > + > +#undef CONFIG_CMD_CRC32 > +#undef CONFIG_BOOTM_NETBSD > + > +#define CONFIG_FSL_ESDHC > +#define CONFIG_FSL_USDHC > +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 > +#define USDHC1_BASE_ADDR 0x5B010000 > +#define USDHC2_BASE_ADDR 0x5B020000 > +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ > + > +#define CONFIG_ENV_OVERWRITE > + > +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG > + > +/* Initial environment variables */ > +#define CONFIG_EXTRA_ENV_SETTINGS \ > + "script=boot.scr\0" \ > + "image=Image\0" \ > + "panel=NULL\0" \ > + "console=ttyLP0,${baudrate} > earlycon=lpuart32,0x5a060000,${baudrate}\0" \ > + "fdt_addr=0x83000000\0" \ > + "fdt_high=0xffffffffffffffff\0" \ > + "boot_fdt=try\0" \ > + "fdt_file=fsl-imx8qxp-mek.dtb\0" \ > + "initrd_addr=0x83800000\0" \ > + "initrd_high=0xffffffffffffffff\0" \ > + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ > + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ > + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ > + "mmcautodetect=yes\0" \ > + "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \ > + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} > ${script};\0" \ > + "bootscript=echo Running bootscript from mmc ...; " \ > + "source\0" \ > + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} > ${image}\0" \ > + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" > \ > + "mmcboot=echo Booting from mmc ...; " \ > + "run mmcargs; " \ > + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ > + "if run loadfdt; then " \ > + "booti ${loadaddr} - ${fdt_addr}; " \ > + "else " \ > + "echo WARN: Cannot load the DT; " \ > + "fi; " \ > + "else " \ > + "echo wait for boot; " \ > + "fi;\0" \ > + "netargs=setenv bootargs console=${console} " \ > + "root=/dev/nfs " \ > + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ > + "netboot=echo Booting from net ...; " \ > + "run netargs; " \ > + "if test ${ip_dyn} = yes; then " \ > + "setenv get_cmd dhcp; " \ > + "else " \ > + "setenv get_cmd tftp; " \ > + "fi; " \ > + "${get_cmd} ${loadaddr} ${image}; " \ > + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ > + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ > + "booti ${loadaddr} - ${fdt_addr}; " \ > + "else " \ > + "echo WARN: Cannot load the DT; " \ > + "fi; " \ > + "else " \ > + "booti; " \ > + "fi;\0" > + > +#define CONFIG_BOOTCOMMAND \ > + "mmc dev ${mmcdev}; if mmc rescan; then " \ > + "if run loadbootscript; then " \ > + "run bootscript; " \ > + "else " \ > + "if run loadimage; then " \ > + "run mmcboot; " \ > + "else run netboot; " \ > + "fi; " \ > + "fi; " \ > + "else booti ${loadaddr} - ${fdt_addr}; fi" > + > +/* Link Definitions */ > +#define CONFIG_LOADADDR 0x80280000 > + > +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR > + > +#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 > + > +/* Default environment is in SD */ > +#define CONFIG_ENV_SIZE 0x1000 > +#define CONFIG_ENV_OFFSET (64 * SZ_64K) > +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ > + > +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 > + > +/* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board > */ > +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ > +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 > */ > +#define CONFIG_SYS_FSL_USDHC_NUM 2 > + > +/* Size of malloc() pool */ > +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) > * 1024) > + > +#define CONFIG_SYS_SDRAM_BASE 0x80000000 > +#define PHYS_SDRAM_1 0x80000000 > +#define PHYS_SDRAM_2 0x880000000 > +#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ > +#define PHYS_SDRAM_2_SIZE 0x100000000 /* 4 GB */ > + > +/* Serial */ > +#define CONFIG_BAUDRATE 115200 > + > +/* Monitor Command Prompt */ > +#define CONFIG_HUSH_PARSER > +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " > +#define CONFIG_SYS_CBSIZE 2048 > +#define CONFIG_SYS_MAXARGS 64 > +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE > +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ > + sizeof(CONFIG_SYS_PROMPT) + 16) > + > +/* Generic Timer Definitions */ > +#define COUNTER_FREQUENCY 8000000 /* 8MHz */ > + > +/* Networking */ > +#define CONFIG_FEC_XCV_TYPE RGMII > +#define FEC_QUIRK_ENET_MAC > + > +#endif /* __IMX8QM_MEK_H */ > -- > 2.16.4
Hi Stefano On Fri, 2019-04-26 at 09:37 +0000, sbabic@denx.de wrote: > > Add i.MX8QM MEK board support. > > Included a basic dts, enabled SPL FIT > > Boot log as below: > > U-Boot SPL 2019.01-rc1-00029-gf002213219 (Dec 24 2018 - 10:28:30 > > +0800) > > Normal Boot > > Trying to boot from MMC2_2 > > U-Boot 2019.01-rc1-00029-gf002213219 (Dec 24 2018 - 10:28:30 +0800) > > CPU: NXP i.MX8QM RevB A53 at 142933 MHz > > Model: Freescale i.MX8QM MEK > > Board: iMX8QM MEK > > Build: SCFW 9330215b > > Boot: SD1 > > DRAM: 6 GiB > > MMC: FSL_SDHC: 0, FSL_SDHC: 1 > > Loading Environment from MMC... *** Warning - bad CRC, using > > default environment > > In: serial@5a060000 > > Out: serial@5a060000 > > Err: serial@5a060000 > > Net: > > Error: ethernet@5b040000 address not set. > > eth-1: ethernet@5b040000 > > Hit any key to stop autoboot: 0 > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > > Applied to u-boot-imx, master, thanks ! This one introduced a superfluous trailing line continuation in the Makefile: https://git.denx.de/?p=u-boot/u-boot-imx.git;a=commitdiff;h=0d331c035a091c1c1af4180b40bd234e3b87e80a#patch1 I will fix this and also make sure stuff is alphabetically sorted again in my updated Colibri iMX8X introduction patch. OK? > Best regards, > Stefano Babic Cheers Marcel
On 26/04/19 12:50, Marcel Ziswiler wrote: > Hi Stefano > > On Fri, 2019-04-26 at 09:37 +0000, sbabic@denx.de wrote: >>> Add i.MX8QM MEK board support. >>> Included a basic dts, enabled SPL FIT >>> Boot log as below: >>> U-Boot SPL 2019.01-rc1-00029-gf002213219 (Dec 24 2018 - 10:28:30 >>> +0800) >>> Normal Boot >>> Trying to boot from MMC2_2 >>> U-Boot 2019.01-rc1-00029-gf002213219 (Dec 24 2018 - 10:28:30 +0800) >>> CPU: NXP i.MX8QM RevB A53 at 142933 MHz >>> Model: Freescale i.MX8QM MEK >>> Board: iMX8QM MEK >>> Build: SCFW 9330215b >>> Boot: SD1 >>> DRAM: 6 GiB >>> MMC: FSL_SDHC: 0, FSL_SDHC: 1 >>> Loading Environment from MMC... *** Warning - bad CRC, using >>> default environment >>> In: serial@5a060000 >>> Out: serial@5a060000 >>> Err: serial@5a060000 >>> Net: >>> Error: ethernet@5b040000 address not set. >>> eth-1: ethernet@5b040000 >>> Hit any key to stop autoboot: 0 >>> Signed-off-by: Peng Fan <peng.fan@nxp.com> >> >> Applied to u-boot-imx, master, thanks ! > > This one introduced a superfluous trailing line continuation in the > Makefile: > > https://git.denx.de/?p=u-boot/u-boot-imx.git;a=commitdiff;h=0d331c035a091c1c1af4180b40bd234e3b87e80a#patch1 > > I will fix this and also make sure stuff is alphabetically sorted again > in my updated Colibri iMX8X introduction patch. OK? That's fine, thanks ! Best regards, Stefano Babic
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 2a040b20a5..954d595391 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -486,7 +486,9 @@ dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \ dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb -dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qxp-mek.dtb +dtb-$(CONFIG_ARCH_IMX8) += \ + fsl-imx8qxp-mek.dtb \ + fsl-imx8qm-mek.dtb \ dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb diff --git a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi new file mode 100644 index 0000000000..5d50eb028e --- /dev/null +++ b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +&mu { + u-boot,dm-spl; +}; + +&clk { + u-boot,dm-spl; +}; + +&iomuxc { + u-boot,dm-spl; +}; + +&pd_lsio { + u-boot,dm-spl; +}; + +&pd_lsio_gpio0 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio1 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio2 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio3 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio4 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio5 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio6 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio7 { + u-boot,dm-spl; +}; + +&pd_conn { + u-boot,dm-spl; +}; + +&pd_conn_sdch0 { + u-boot,dm-spl; +}; + +&pd_conn_sdch1 { + u-boot,dm-spl; +}; + +&pd_conn_sdch2 { + u-boot,dm-spl; +}; + +&gpio0 { + u-boot,dm-spl; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&gpio5 { + u-boot,dm-spl; +}; + +&gpio6 { + u-boot,dm-spl; +}; + +&gpio7 { + u-boot,dm-spl; +}; + +&lpuart0 { + u-boot,dm-spl; +}; + +&usdhc1 { + u-boot,dm-spl; +}; + +&usdhc2 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/fsl-imx8qm-mek.dts b/arch/arm/dts/fsl-imx8qm-mek.dts new file mode 100644 index 0000000000..63908ba6bf --- /dev/null +++ b/arch/arm/dts/fsl-imx8qm-mek.dts @@ -0,0 +1,184 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017-2018 NXP + */ + +/dts-v1/; + +#include "fsl-imx8qm.dtsi" +#include "fsl-imx8qm-mek-u-boot.dtsi" + +/ { + model = "Freescale i.MX8QM MEK"; + compatible = "fsl,imx8qm-mek", "fsl,imx8qm"; + + chosen { + bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200"; + stdout-path = &lpuart0; + }; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "sw-3p3-sd1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; + off-on-delay = <4800>; + enable-active-high; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx8qm-mek { + pinctrl_hog: hoggrp { + fsl,pins = < + SC_P_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0x0600004c + SC_P_QSPI1A_DATA1_LSIO_GPIO4_IO25 0x0600004c + SC_P_SCU_GPIO0_03_LSIO_GPIO0_IO31 0x0600004c + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 + SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000061 + SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000061 + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000061 + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000061 + SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000061 + SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000061 + SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000061 + SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000061 + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000061 + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000061 + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000061 + SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000061 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0 + SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060 + SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060 + SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060 + SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060 + SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060 + SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060 + SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060 + SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060 + SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060 + SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060 + SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060 + SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + SC_P_UART0_RX_DMA_UART0_RX 0x06000020 + SC_P_UART0_TX_DMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021 + SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021 + SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + }; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy0>; + fsl,magic-packet; + fsl,rgmii_rxc_dly; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + at803x,eee-disabled; + at803x,vddio-1p8v; + status = "disabled"; + }; + }; +}; + +&lpuart0 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index 4336a8c236..c32f7dbb61 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -32,8 +32,14 @@ config TARGET_IMX8QXP_MEK select BOARD_LATE_INIT select IMX8QXP +config TARGET_IMX8QM_MEK + bool "Support i.MX8QM MEK board" + select BOARD_LATE_INIT + select IMX8QM + endchoice source "board/freescale/imx8qxp_mek/Kconfig" +source "board/freescale/imx8qm_mek/Kconfig" endif diff --git a/board/freescale/imx8qm_mek/Kconfig b/board/freescale/imx8qm_mek/Kconfig new file mode 100644 index 0000000000..93d7d5f9c5 --- /dev/null +++ b/board/freescale/imx8qm_mek/Kconfig @@ -0,0 +1,14 @@ +if TARGET_IMX8QM_MEK + +config SYS_BOARD + default "imx8qm_mek" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "imx8qm_mek" + +source "board/freescale/common/Kconfig" + +endif diff --git a/board/freescale/imx8qm_mek/MAINTAINERS b/board/freescale/imx8qm_mek/MAINTAINERS new file mode 100644 index 0000000000..115830df19 --- /dev/null +++ b/board/freescale/imx8qm_mek/MAINTAINERS @@ -0,0 +1,6 @@ +i.MX8QM MEK BOARD +M: Peng Fan <peng.fan@nxp.com> +S: Maintained +F: board/freescale/imx8qm_mek/ +F: include/configs/imx8qm_mek.h +F: configs/imx8qm_mek_defconfig diff --git a/board/freescale/imx8qm_mek/Makefile b/board/freescale/imx8qm_mek/Makefile new file mode 100644 index 0000000000..bc9a1260bd --- /dev/null +++ b/board/freescale/imx8qm_mek/Makefile @@ -0,0 +1,8 @@ +# +# Copyright 2018 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx8qm_mek.o +obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/board/freescale/imx8qm_mek/README b/board/freescale/imx8qm_mek/README new file mode 100644 index 0000000000..c3523801ae --- /dev/null +++ b/board/freescale/imx8qm_mek/README @@ -0,0 +1,57 @@ +U-Boot for the NXP i.MX8QM EVK board + +Quick Start +=========== + +- Build the ARM Trusted firmware binary +- Get scfw_tcm.bin and ahab-container.img +- Build U-Boot +- Flash the binary into the SD card +- Boot + +Get and Build the ARM Trusted firmware +====================================== + +$ git clone https://source.codeaurora.org/external/imx/imx-atf +$ cd imx-atf/ +$ git checkout origin/imx_4.14.78_1.0.0_ga -b imx_4.14.78_1.0.0_ga +$ make PLAT=imx8qm bl31 + +Get scfw_tcm.bin and ahab-container.img +============================== + +$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-sc-firmware-1.1.bin +$ chmod +x imx-sc-firmware-1.1.bin +$ ./imx-sc-firmware-1.1.bin +$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin +$ chmod +x firmware-imx-8.0.bin +$ ./firmware-imx-8.0.bin + +Copy the following binaries to U-Boot folder: + +$ cp imx-atf/build/imx8qm/release/bl31.bin . +$ cp u-boot/u-boot.bin . + +Copy the following firmwares U-Boot folder : + +$ cp firmware-imx-7.6/firmware/seco/ahab-container.img . +$ cp imx-sc-firmware-0.7/mx8qm-mek-scfw-tcm.bin . + +Build U-Boot +============ +$ export ATF_LOAD_ADDR=0x80000000 +$ export BL33_LOAD_ADDR=0x80020000 +$ make imx8qm_mek_defconfig +$ make flash.bin +$ dd if=u-boot.itb of=flash.bin bs=512 seek=1984 + +Flash the binary into the SD card +================================= + +Burn the flash.bin binary to SD card offset 32KB: + +$ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32 + +Boot +==== +Set Boot switch SW2: 1100. diff --git a/board/freescale/imx8qm_mek/imx8qm_mek.c b/board/freescale/imx8qm_mek/imx8qm_mek.c new file mode 100644 index 0000000000..e69efc4dd6 --- /dev/null +++ b/board/freescale/imx8qm_mek/imx8qm_mek.c @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include <common.h> +#include <errno.h> +#include <linux/libfdt.h> +#include <environment.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <asm/arch/clock.h> +#include <asm/arch/sci/sci.h> +#include <asm/arch/imx8-pins.h> +#include <asm/arch/iomux.h> +#include <asm/arch/sys_proto.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +static iomux_cfg_t uart0_pads[] = { + SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads)); +} + +int board_early_init_f(void) +{ + int ret; + /* Set UART0 clock root to 80 MHz */ + sc_pm_clock_rate_t rate = 80000000; + + /* Power up UART0 */ + ret = sc_pm_set_resource_power_mode(-1, SC_R_UART_0, SC_PM_PW_MODE_ON); + if (ret) + return ret; + + ret = sc_pm_set_clock_rate(-1, SC_R_UART_0, 2, &rate); + if (ret) + return ret; + + /* Enable UART0 clock root */ + ret = sc_pm_clock_enable(-1, SC_R_UART_0, 2, true, false); + if (ret) + return ret; + + setup_iomux_uart(); + + sc_pm_set_resource_power_mode(-1, SC_R_GPIO_5, SC_PM_PW_MODE_ON); + + return 0; +} + +#if IS_ENABLED(CONFIG_DM_GPIO) +static void board_gpio_init(void) +{ + /* TODO */ +} +#else +static inline void board_gpio_init(void) {} +#endif + +#if IS_ENABLED(CONFIG_FEC_MXC) +#include <miiphy.h> + +int board_phy_config(struct phy_device *phydev) +{ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +void build_info(void) +{ + u32 sc_build = 0, sc_commit = 0; + + /* Get SCFW build and commit id */ + sc_misc_build_info(-1, &sc_build, &sc_commit); + if (!sc_build) { + printf("SCFW does not support build info\n"); + sc_commit = 0; /* Display 0 when the build info is not supported*/ + } + printf("Build: SCFW %x\n", sc_commit); +} + +int checkboard(void) +{ + puts("Board: iMX8QM MEK\n"); + + build_info(); + print_bootinfo(); + + return 0; +} + +int board_init(void) +{ + /* Power up base board */ + sc_pm_set_resource_power_mode(-1, SC_R_BOARD_R1, SC_PM_PW_MODE_ON); + + board_gpio_init(); + + return 0; +} + +void detail_board_ddr_info(void) +{ + puts("\nDDR "); +} + +/* + * Board specific reset that is system reset. + */ +void reset_cpu(ulong addr) +{ + /* TODO */ +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, bd_t *bd) +{ + return 0; +} +#endif + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + env_set("board_name", "MEK"); + env_set("board_rev", "iMX8QM"); +#endif + + return 0; +} diff --git a/board/freescale/imx8qm_mek/imximage.cfg b/board/freescale/imx8qm_mek/imximage.cfg new file mode 100644 index 0000000000..7dc6b93eb5 --- /dev/null +++ b/board/freescale/imx8qm_mek/imximage.cfg @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#define __ASSEMBLY__ + +/* Boot from SD, sector size 0x400 */ +BOOT_FROM SD 0x400 +/* SoC type IMX8QM */ +SOC_TYPE IMX8QM +/* Append seco container image */ +APPEND mx8qm-ahab-container.img +/* Create the 2nd container */ +CONTAINER +/* Add scfw image with exec attribute */ +IMAGE SCU mx8qm-mek-scfw-tcm.bin +/* Add ATF image with exec attribute */ +IMAGE A35 spl/u-boot-spl.bin 0x00100000 diff --git a/board/freescale/imx8qm_mek/spl.c b/board/freescale/imx8qm_mek/spl.c new file mode 100644 index 0000000000..95ce9f37e8 --- /dev/null +++ b/board/freescale/imx8qm_mek/spl.c @@ -0,0 +1,75 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <spl.h> +#include <dm/uclass.h> +#include <dm/device.h> +#include <dm/uclass-internal.h> +#include <dm/device-internal.h> +#include <dm/lists.h> + +DECLARE_GLOBAL_DATA_PTR; + +void spl_board_init(void) +{ + struct udevice *dev; + int offset; + + uclass_find_first_device(UCLASS_MISC, &dev); + + for (; dev; uclass_find_next_device(&dev)) { + if (device_probe(dev)) + continue; + } + + offset = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "nxp,imx8-pd"); + while (offset != -FDT_ERR_NOTFOUND) { + lists_bind_fdt(gd->dm_root, offset_to_ofnode(offset), + NULL, true); + offset = fdt_node_offset_by_compatible(gd->fdt_blob, offset, + "nxp,imx8-pd"); + } + + uclass_find_first_device(UCLASS_POWER_DOMAIN, &dev); + + for (; dev; uclass_find_next_device(&dev)) { + if (device_probe(dev)) + continue; + } + + arch_cpu_init(); + + board_early_init_f(); + + timer_init(); + + preloader_console_init(); + + puts("Normal Boot\n"); +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif + +void board_init_f(ulong dummy) +{ + /* Clear global data */ + memset((void *)gd, 0, sizeof(gd_t)); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + board_init_r(NULL, 0); +} diff --git a/configs/imx8qm_mek_defconfig b/configs/imx8qm_mek_defconfig new file mode 100644 index 0000000000..238d44d1f5 --- /dev/null +++ b/configs/imx8qm_mek_defconfig @@ -0,0 +1,75 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_IMX8QM_MEK=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_NR_DRAM_BANKS=3 +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qm_mek/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_LOG=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_CMD_CPU=y +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_FAT=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_DM_GPIO=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set diff --git a/include/configs/imx8qm_mek.h b/include/configs/imx8qm_mek.h new file mode 100644 index 0000000000..02c5d1c054 --- /dev/null +++ b/include/configs/imx8qm_mek.h @@ -0,0 +1,176 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __IMX8QM_MEK_H +#define __IMX8QM_MEK_H + +#include <linux/sizes.h> +#include <asm/arch/imx-regs.h> + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_TEXT_BASE 0x0 +#define CONFIG_SPL_MAX_SIZE (124 * 1024) +#define CONFIG_SYS_MONITOR_LEN (1024 * 1024) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x800 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 0 + +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +#define CONFIG_SPL_STACK 0x013E000 +#define CONFIG_SPL_BSS_START_ADDR 0x00128000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x00120000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */ +#define CONFIG_SERIAL_LPUART_BASE 0x5a060000 +#define CONFIG_SYS_ICACHE_OFF +#define CONFIG_SYS_DCACHE_OFF +#define CONFIG_MALLOC_F_ADDR 0x00120000 + +#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE + +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE + +#define CONFIG_OF_EMBED +#endif + +#define CONFIG_REMAKE_ELF + +#define CONFIG_BOARD_EARLY_INIT_F + +/* Flat Device Tree Definitions */ +#define CONFIG_OF_BOARD_SETUP + +#undef CONFIG_CMD_EXPORTENV +#undef CONFIG_CMD_IMPORTENV +#undef CONFIG_CMD_IMLS + +#undef CONFIG_CMD_CRC32 +#undef CONFIG_BOOTM_NETBSD + +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define USDHC1_BASE_ADDR 0x5B010000 +#define USDHC2_BASE_ADDR 0x5B020000 +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ + +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=Image\0" \ + "panel=NULL\0" \ + "console=ttyLP0,${baudrate} earlycon=lpuart32,0x5a060000,${baudrate}\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "boot_fdt=try\0" \ + "fdt_file=fsl-imx8qxp-mek.dtb\0" \ + "initrd_addr=0x83800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "echo wait for boot; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "booti; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else booti ${loadaddr} - ${fdt_addr}; fi" + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x80280000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 + +/* Default environment is in SD */ +#define CONFIG_ENV_SIZE 0x1000 +#define CONFIG_ENV_OFFSET (64 * SZ_64K) +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +/* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */ +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_2 0x880000000 +#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ +#define PHYS_SDRAM_2_SIZE 0x100000000 /* 4 GB */ + +/* Serial */ +#define CONFIG_BAUDRATE 115200 + +/* Monitor Command Prompt */ +#define CONFIG_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 8000000 /* 8MHz */ + +/* Networking */ +#define CONFIG_FEC_XCV_TYPE RGMII +#define FEC_QUIRK_ENET_MAC + +#endif /* __IMX8QM_MEK_H */
Add i.MX8QM MEK board support. Included a basic dts, enabled SPL FIT Boot log as below: U-Boot SPL 2019.01-rc1-00029-gf002213219 (Dec 24 2018 - 10:28:30 +0800) Normal Boot Trying to boot from MMC2_2 U-Boot 2019.01-rc1-00029-gf002213219 (Dec 24 2018 - 10:28:30 +0800) CPU: NXP i.MX8QM RevB A53 at 142933 MHz Model: Freescale i.MX8QM MEK Board: iMX8QM MEK Build: SCFW 9330215b Boot: SD1 DRAM: 6 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 Loading Environment from MMC... *** Warning - bad CRC, using default environment In: serial@5a060000 Out: serial@5a060000 Err: serial@5a060000 Net: Error: ethernet@5b040000 address not set. eth-1: ethernet@5b040000 Hit any key to stop autoboot: 0 Signed-off-by: Peng Fan <peng.fan@nxp.com> --- arch/arm/dts/Makefile | 4 +- arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi | 112 +++++++++++++++++++ arch/arm/dts/fsl-imx8qm-mek.dts | 184 ++++++++++++++++++++++++++++++++ arch/arm/mach-imx/imx8/Kconfig | 6 ++ board/freescale/imx8qm_mek/Kconfig | 14 +++ board/freescale/imx8qm_mek/MAINTAINERS | 6 ++ board/freescale/imx8qm_mek/Makefile | 8 ++ board/freescale/imx8qm_mek/README | 57 ++++++++++ board/freescale/imx8qm_mek/imx8qm_mek.c | 157 +++++++++++++++++++++++++++ board/freescale/imx8qm_mek/imximage.cfg | 19 ++++ board/freescale/imx8qm_mek/spl.c | 75 +++++++++++++ configs/imx8qm_mek_defconfig | 75 +++++++++++++ include/configs/imx8qm_mek.h | 176 ++++++++++++++++++++++++++++++ 13 files changed, 892 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi create mode 100644 arch/arm/dts/fsl-imx8qm-mek.dts create mode 100644 board/freescale/imx8qm_mek/Kconfig create mode 100644 board/freescale/imx8qm_mek/MAINTAINERS create mode 100644 board/freescale/imx8qm_mek/Makefile create mode 100644 board/freescale/imx8qm_mek/README create mode 100644 board/freescale/imx8qm_mek/imx8qm_mek.c create mode 100644 board/freescale/imx8qm_mek/imximage.cfg create mode 100644 board/freescale/imx8qm_mek/spl.c create mode 100644 configs/imx8qm_mek_defconfig create mode 100644 include/configs/imx8qm_mek.h