diff mbox

[U-Boot,v2] ARM: mx31: Print the silicon version

Message ID 1302491295-11222-1-git-send-email-festevam@gmail.com
State Changes Requested
Headers show

Commit Message

Fabio Estevam April 11, 2011, 3:08 a.m. UTC 
Use the same method of the Linux kernel to print the MX31 silicon version on 
boot.

Tested on a MX31PDK with a 2.0 silicon, where it shows:

CPU:   Freescale i.MX31 at 531 MHz
MX31 silicon rev 2.0

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
Changes since v1:
- rename the CPU detect function name to get_cpu_rev
- Use struct to access iim register

 arch/arm/cpu/arm1136/mx31/generic.c       |   18 ++++++++++++
 arch/arm/include/asm/arch-mx31/imx-regs.h |   20 +++++++++++++
 arch/arm/include/asm/imx_soc_revision.h   |   42 +++++++++++++++++++++++++++++
 3 files changed, 80 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/include/asm/imx_soc_revision.h

Comments

Wolfgang Denk April 11, 2011, 10:16 a.m. UTC | #1 
Dear Fabio Estevam,

In message <1302491295-11222-1-git-send-email-festevam@gmail.com> you wrote:
> Use the same method of the Linux kernel to print the MX31 silicon version on 
> boot.
> 
> Tested on a MX31PDK with a 2.0 silicon, where it shows:
> 
> CPU:   Freescale i.MX31 at 531 MHz
...
> +#define IMX_CHIP_REVISION_1_0		0x10
> +#define IMX_CHIP_REVISION_1_1		0x11
> +#define IMX_CHIP_REVISION_1_2		0x12
> +#define IMX_CHIP_REVISION_1_3		0x13
> +#define IMX_CHIP_REVISION_2_0		0x20
> +#define IMX_CHIP_REVISION_2_1		0x21
> +#define IMX_CHIP_REVISION_2_2		0x22
> +#define IMX_CHIP_REVISION_2_3		0x23
> +#define IMX_CHIP_REVISION_3_0		0x30
> +#define IMX_CHIP_REVISION_3_1		0x31
> +#define IMX_CHIP_REVISION_3_2		0x32
> +#define IMX_CHIP_REVISION_3_3		0x33

What a nightmare.  Does this not give the creeps to any of you who add
to this code?

I'm finally fed up with this, and say NAK here.

Please use something like this instead:

	#define IMX_CHIP_REVISION(maj, min) ((maj) * 16 + (min))

Feel free to add appropriate range checking on the parameters,
probably using BUILD_BUG_ON() so it gets caught at compile time.

Best regards,

Wolfgang Denk
diff mbox

Patch

diff --git a/arch/arm/cpu/arm1136/mx31/generic.c b/arch/arm/cpu/arm1136/mx31/generic.c
index fa07fec..cfcb3d8 100644
--- a/arch/arm/cpu/arm1136/mx31/generic.c
+++ b/arch/arm/cpu/arm1136/mx31/generic.c
@@ -24,6 +24,7 @@ 
 #include <common.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/io.h>
+#include <asm/imx_soc_revision.h>
 
 static u32 mx31_decode_pll(u32 reg, u32 infreq)
 {
@@ -106,11 +107,28 @@  void mx31_set_pad(enum iomux_pins pin, u32 config)
 
 }
 
+void get_cpu_rev(void)
+{
+	u32 i, srev;
+
+	/* read SREV register from IIM module */
+	struct iim_regs *iim = (struct iim_regs *)MX31_IIM_BASE_ADDR;
+	srev = readl(&iim->iim_srev);
+
+	for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
+		if (srev == mx31_cpu_type[i].srev) {
+			printf("MX31 silicon rev %s\n", mx31_cpu_type[i].v);
+				return;
+		}
+	printf("Unknown CPU identifier. srev = %02x\n", srev);
+}
+
 #if defined(CONFIG_DISPLAY_CPUINFO)
 int print_cpuinfo (void)
 {
 	printf("CPU:   Freescale i.MX31 at %d MHz\n",
 		mx31_get_mcu_main_clk() / 1000000);
+	get_cpu_rev();
 	return 0;
 }
 #endif
diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h
index 37337f2..6401a37 100644
--- a/arch/arm/include/asm/arch-mx31/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx31/imx-regs.h
@@ -84,6 +84,24 @@  struct wdog_regs {
 	u16 wrsr;	/* Reset Status */
 };
 
+/* IIM Control Registers */
+struct iim_regs {
+	u32 iim_stat;
+	u32 iim_statm;
+	u32 iim_err;
+	u32 iim_emask;
+	u32 iim_fctl;
+	u32 iim_ua;
+	u32 iim_la;
+	u32 iim_sdat;
+	u32 iim_prev;
+	u32 iim_srev;
+	u32 iim_prog_p;
+	u32 iim_scs0;
+	u32 iim_scs1;
+	u32 iim_scs2;
+	u32 iim_scs3;
+};
 
 #define IOMUX_PADNUM_MASK	0x1ff
 #define IOMUX_PIN(gpionum, padnum) ((padnum) & IOMUX_PADNUM_MASK)
@@ -480,6 +498,8 @@  enum iomux_pins {
 #define CCMR_FPM	(1 << 1)
 #define CCMR_CKIH	(2 << 1)
 
+#define MX31_IIM_BASE_ADDR	0x5001C000
+
 #define PDR0_CSI_PODF(x)	(((x) & 0x1ff) << 23)
 #define PDR0_PER_PODF(x)	(((x) & 0x1f) << 16)
 #define PDR0_HSP_PODF(x)	(((x) & 0x7) << 11)
diff --git a/arch/arm/include/asm/imx_soc_revision.h b/arch/arm/include/asm/imx_soc_revision.h
new file mode 100644
index 0000000..0179d52
--- /dev/null
+++ b/arch/arm/include/asm/imx_soc_revision.h
@@ -0,0 +1,42 @@ 
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ *
+ * Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ */
+
+#define IMX_CHIP_REVISION_1_0		0x10
+#define IMX_CHIP_REVISION_1_1		0x11
+#define IMX_CHIP_REVISION_1_2		0x12
+#define IMX_CHIP_REVISION_1_3		0x13
+#define IMX_CHIP_REVISION_2_0		0x20
+#define IMX_CHIP_REVISION_2_1		0x21
+#define IMX_CHIP_REVISION_2_2		0x22
+#define IMX_CHIP_REVISION_2_3		0x23
+#define IMX_CHIP_REVISION_3_0		0x30
+#define IMX_CHIP_REVISION_3_1		0x31
+#define IMX_CHIP_REVISION_3_2		0x32
+#define IMX_CHIP_REVISION_3_3		0x33
+#define IMX_CHIP_REVISION_UNKNOWN	0xff
+
+struct mx3_cpu_type {
+	u8 srev;
+	const char *name;
+	const char *v;
+	unsigned int rev;
+};
+
+struct mx3_cpu_type mx31_cpu_type[] = {
+	{ .srev = 0x00, .name = "i.MX31(L)", .v = "1.0",  .rev = IMX_CHIP_REVISION_1_0  },
+	{ .srev = 0x10, .name = "i.MX31",    .v = "1.1",  .rev = IMX_CHIP_REVISION_1_1	},
+	{ .srev = 0x11, .name = "i.MX31L",   .v = "1.1",  .rev = IMX_CHIP_REVISION_1_1	},
+	{ .srev = 0x12, .name = "i.MX31",    .v = "1.15", .rev = IMX_CHIP_REVISION_1_1	},
+	{ .srev = 0x13, .name = "i.MX31L",   .v = "1.15", .rev = IMX_CHIP_REVISION_1_1	},
+	{ .srev = 0x14, .name = "i.MX31",    .v = "1.2",  .rev = IMX_CHIP_REVISION_1_2	},
+	{ .srev = 0x15, .name = "i.MX31L",   .v = "1.2",  .rev = IMX_CHIP_REVISION_1_2	},
+	{ .srev = 0x28, .name = "i.MX31",    .v = "2.0",  .rev = IMX_CHIP_REVISION_2_0	},
+	{ .srev = 0x29, .name = "i.MX31L",   .v = "2.0",  .rev = IMX_CHIP_REVISION_2_0	},
+};