new file mode 100644
@@ -0,0 +1,53 @@
+#
+# Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
+#
+# Based on original Kirkwood support which is
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := dns323_b1.o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+clean:
+ rm -f $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
new file mode 100644
@@ -0,0 +1,28 @@
+#
+# Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+# TEXT_BASE must equal the intended FLASH location of u-boot.
+CONFIG_SYS_TEXT_BASE = 0xfffd0000
new file mode 100644
@@ -0,0 +1,78 @@
+/*
+ * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
+ *
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/orion5x.h>
+#include "dns323_b1.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ /* arch number of board */
+ gd->bd->bi_arch_number = MACH_TYPE_DNS323;
+
+ /* boot parameter start at 256th byte of RAM base */
+ gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
+
+ return 0;
+}
+
+#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
+/* Configure and enable MV88E1116 PHY */
+void reset_phy(void)
+{
+ u16 reg;
+ u16 devadr;
+ char *name = "egiga0";
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /* command to read PHY dev address */
+ if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
+ printf("Err..%s could not read PHY dev address\n",
+ __func__);
+ return;
+ }
+
+ /*
+ * Enable RGMII delay on Tx and Rx for CPU port
+ * Ref: sec 4.7.2 of chip datasheet
+ */
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
+ miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
+ reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
+ miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+
+ /* reset the phy */
+ miiphy_reset(name, devadr);
+
+ printf("88E1116 Initialized on %s\n", name);
+}
+#endif /* CONFIG_RESET_PHY_R */
new file mode 100644
@@ -0,0 +1,41 @@
+/*
+ * (C) Copyright 2009
+ * Net Insight <www.netinsight.net>
+ * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
+ *
+ * Based on sheevaplug.h:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __DNS323_BASE_H
+#define __DNS323_BASE_H
+
+/* PHY related */
+#define MV88E1116_LED_FCTRL_REG 10
+#define MV88E1116_CPRSP_CR3_REG 21
+#define MV88E1116_MAC_CTRL_REG 21
+#define MV88E1116_PGADR_REG 22
+#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
+
+#endif /* __DNS323_BASE_H */
@@ -104,6 +104,7 @@ jadecpu arm arm926ejs jadecpu syteco
imx27lite arm arm926ejs imx27lite logicpd mx27
magnesium arm arm926ejs imx27lite logicpd mx27
omap5912osk arm arm926ejs - ti omap
+dns323_b1 arm arm926ejs - D-Link orion5x
edminiv2 arm arm926ejs - LaCie orion5x
dkb arm arm926ejs - Marvell pantheon
ca9x4_ct_vxp arm armv7 vexpress armltd
new file mode 100644
@@ -0,0 +1,270 @@
+/*
+ * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
+ *
+ * Based on original Kirkwood support which is
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _CONFIG_DNS323_B1_H
+#define _CONFIG_DNS323_B1_H
+
+/*
+ * Version number information
+ */
+
+#define CONFIG_IDENT_STRING " DNS323B1"
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+
+#define CONFIG_MARVELL 1
+#define CONFIG_ARM926EJS 1 /* Basic Architecture */
+#define CONFIG_FEROCEON 1 /* CPU Core subversion */
+#define CONFIG_ORION5X 1 /* SOC Family Name */
+#define CONFIG_88F5182 1 /* SOC Name */
+#define CONFIG_MACH_DNS323 1 /* Machine type */
+#define CONFIG_MARVELL_TAG /* Match Vendor U-Boot */
+
+/* Skip lowlevel init -
+ * makes an image suitable for chaining from another u-boot loader
+ * This config has not been tested for flashing
+ */
+#define CONFIG_SKIP_LOWLEVEL_INIT 1
+
+/*
+ * CLKs configurations
+ */
+
+#define CONFIG_SYS_HZ 1000
+
+/*
+ * Board-specific values for Orion5x MPP low level init:
+ * - MPPs 12 to 15 are SATA LEDs (mode 5)
+ * - Others are GPIO/unused (mode 3 for MPP0, mode 5 for
+ * MPP16 to MPP19, mode 0 for others
+ *
+ * Settings for DNS323 B1 have not been determined, set all to 0
+ */
+
+#define ORION5X_MPP0_7 0x00000000
+#define ORION5X_MPP8_15 0x00000000
+#define ORION5X_MPP16_23 0x00000000
+
+/*
+ * Board-specific values for Orion5x GPIO low level init:
+ * - GPIO3 is input (RTC interrupt)
+ * - GPIO16 is Power LED control (0 = on, 1 = off)
+ * - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16)
+ * - GPIO18 is Power Button status (0 = Released, 1 = Pressed)
+ * - Last GPIO is 26, further bits are supposed to be 0.
+ * Enable mask has ones for INPUT, 0 for OUTPUT.
+ * Default is LED ON.
+ */
+
+#define ORION5X_GPIO_OUT_ENABLE 0x00000000
+#define ORION5X_GPIO_OUT_VALUE 0x00000000
+
+/*
+ * NS16550 Configuration
+ */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
+#define CONFIG_SYS_NS16550_COM1 ORION5X_UART0_BASE
+
+/*
+ * Serial Port configuration
+ * The following definitions let you select what serial you want to use
+ * for your console driver.
+ */
+
+#define CONFIG_CONS_INDEX 1 /*Console on UART0 */
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ { 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 }
+
+/*
+ * FLASH configuration
+ */
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 135 /* max num of sects on one chip */
+#define CONFIG_SYS_FLASH_BASE 0xff800000
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+
+#define ORION5X_ADR_BOOTROM CONFIG_SYS_FLASH_BASE
+#define ORION5X_SZ_BOOTROM (8 * 1024 * 1024)
+
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
+#define CONFIG_SYS_FLASH_PROTECTION 1
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+/* auto boot */
+#define CONFIG_BOOTDELAY -1 /* default disable autoboot */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */
+#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */
+
+#define CONFIG_SYS_PROMPT "DNS323B1> " /* Command Prompt */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
+ +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */
+/*
+ * Commands configuration - using default command set for now
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_I2C
+
+/*
+ * Network
+ */
+
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE /* Enable Marvell GbE Driver */
+#define CONFIG_MVGBE_PORTS {1} /* enable port 0 only */
+#define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION /* don't randomize MAC */
+#define CONFIG_PHY_BASE_ADR 0x8
+#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */
+#define CONFIG_NETCONSOLE /* include NetConsole support */
+#define CONFIG_NET_MULTI /* specify more that one ports available */
+#define CONFIG_MII /* expose smi ove miiphy interface */
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
+#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
+#define CONFIG_CMD_DHCP
+#endif
+
+/*
+ * IDE
+ */
+#ifdef CONFIG_CMD_IDE
+#define __io
+#define CONFIG_IDE_PREINIT
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+/* ED Mini V has an IDE-compatible SATA connector for port 1 */
+#define CONFIG_MVSATA_IDE
+#define CONFIG_MVSATA_IDE_USE_PORT1
+/* Needs byte-swapping for ATA data register */
+#define CONFIG_IDE_SWAP_IO
+/* Data, registers and alternate blocks are at the same offset */
+#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100)
+#define CONFIG_SYS_ATA_REG_OFFSET (0x0100)
+#define CONFIG_SYS_ATA_ALT_OFFSET (0x0100)
+/* Each 8-bit ATA register is aligned to a 4-bytes address */
+#define CONFIG_SYS_ATA_STRIDE 4
+/* Controller supports 48-bits LBA addressing */
+#define CONFIG_LBA48
+/* A single bus, a single device */
+#define CONFIG_SYS_IDE_MAXBUS 2
+#define CONFIG_SYS_IDE_MAXDEVICE 2
+/* ATA registers base is at SATA controller base */
+#define CONFIG_SYS_ATA_BASE_ADDR ORION5X_SATA_BASE
+#define CONFIG_SYS_ATA_IDE0_OFFSET ORION5X_SATA_PORT0_OFFSET
+#define CONFIG_SYS_ATA_IDE1_OFFSET ORION5X_SATA_PORT1_OFFSET
+/* end of IDE defines */
+#endif /* CMD_IDE */
+
+/*
+ * I2C related stuff
+ */
+#ifdef CONFIG_CMD_I2C
+#define CONFIG_I2C_MVTWSI
+#define CONFIG_I2C_MVTWSI_BASE ORION5X_TWSI_BASE
+#define CONFIG_SYS_I2C_SLAVE 0x0
+#define CONFIG_SYS_I2C_SPEED 100000
+#endif
+
+/*
+ * Environment variables configurations
+ *
+ * NB: If you save environment variables, they will overwrite
+ * the configuration saved by the vendor firmware, and will in turn
+ * be overwritten by vendor firmware if executed. Only save U-Boot
+ * environment variables if you are not using the vendor firmware.
+ * Unfortunately, vendor U-Boot did not make place for saving the
+ * environment.
+ */
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_SECT_SIZE 0x2000 /* 16K */
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_OFFSET 0x0000 /* env starts here */
+
+#define CONFIG_BOOTARGS "root=/dev/ram console=ttyS0,115200 :::DB88FXX81:egiga0:none"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "bootcmd=bootm FF820000 FF9A0000\0" \
+ "machid=20e\0"
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (1024 * 128) /* 128kB for malloc() */
+/* size in bytes reserved for initial data */
+
+/*
+ * Other required minimal configurations
+ */
+#define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */
+#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
+#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */
+#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */
+#define CONFIG_NR_DRAM_BANKS 4 /* Match vendor U-Boot */
+
+#define CONFIG_STACKSIZE 0x00100000
+#define CONFIG_SYS_LOAD_ADDR 0x00800000
+#define CONFIG_SYS_MEMTEST_START 0x00400000
+#define CONFIG_SYS_MEMTEST_END 0x007fffff
+#define CONFIG_SYS_RESET_ADDRESS 0xffff0000
+#define CONFIG_SYS_MAXARGS 16
+
+/* additions for new relocation code, must be added to all boards */
+#define CONFIG_SYS_SDRAM_BASE 0
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_LONGHELP
+
+#undef CONFIG_CONSOLE_INFO_QUIET
+
+// test-only: nice to have...
+#define CONFIG_CMDLINE_EDITING /* add command line history */
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
+
+#endif /* _CONFIG_DNS323_B1_H */
From: Rogan Dawes <rogan@dawes.za.net> Based on that of the edminiv2, with a few additions The image is configured to boot vendor kernels seamlessly. i.e. the kernel boot logs should be identical between the vendor bootloader and this mainline version. Note that the vendor flash layout does not allow space for saving environment variables. All env variables are compiled in to the vendor bootloader, and saveenv is not provided. According to the flash layout, the smallest segments are at the start of the flash chip, which conflicts with mtd0, used to save the NAS configuration by the vendor firmware. Consequently, if you intend to keep the vendor firmware, do not save any additional environment variables, or change existing ones. GPIO pins are not configured, as they do not match the layout for the EDMiniv2. That configuration causes the kernel to shutdown, as it detects that the power button is pressed. --- board/D-Link/dns323_b1/Makefile | 53 +++++++ board/D-Link/dns323_b1/config.mk | 28 ++++ board/D-Link/dns323_b1/dns323_b1.c | 78 +++++++++++ board/D-Link/dns323_b1/dns323_b1.h | 41 ++++++ boards.cfg | 1 + include/configs/dns323_b1.h | 270 ++++++++++++++++++++++++++++++++++++ 6 files changed, 471 insertions(+), 0 deletions(-) create mode 100644 board/D-Link/dns323_b1/Makefile create mode 100644 board/D-Link/dns323_b1/config.mk create mode 100644 board/D-Link/dns323_b1/dns323_b1.c create mode 100644 board/D-Link/dns323_b1/dns323_b1.h create mode 100644 include/configs/dns323_b1.h