| Message ID | 1548843970-8473-1-git-send-email-ahmet.celenk@procenne.com |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | mtd: spi-nor: split s25fl128s into s25fl128s0 and s25fl128s1 | expand |
On 1/30/19 11:26 AM, A. Celenk wrote: > Due to two different versions (S25FL128SAGBHI200 and S25FL128SAGBHI210) of > the s25fl128s qspi memory, the single "s25fl128s" device entry must be > split into two to match the correct JEDEC ID's for each version. Solves > paging related issues of S25FL128SAGBHI210 chips. > > Signed-off-by: A. Celenk <ahmet.celenk@procenne.com> > Drop this newline. Subject should now contain [PATCH V2] ... > Cc: Boris Brezillon <boris.brezillon@free-electrons.com> > Cc: Marek Vasut <marek.vasut@gmail.com> > --- There should be a changelog describing what changed, like this: V2: - Foo changed - Bar was added Otherwise looks OK to me. > drivers/mtd/spi-nor/spi-nor.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c > index 13a5055..1ee2d56 100644 > --- a/drivers/mtd/spi-nor/spi-nor.c > +++ b/drivers/mtd/spi-nor/spi-nor.c > @@ -1898,7 +1898,8 @@ static const struct flash_info spi_nor_ids[] = { > { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) }, > { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) }, > { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) }, > - { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, > + { "s25fl128s0", INFO6(0x012018, 0x4d0080, 256 * 1024, 64, SPI_NOR_QUAD_READ | USE_CLSR) }, > + { "s25fl128s1", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_QUAD_READ | USE_CLSR) }, > { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, > { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, > { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) }, >
On 30.01.19 11:26, A. Celenk wrote: > Due to two different versions (S25FL128SAGBHI200 and S25FL128SAGBHI210) of > the s25fl128s qspi memory, the single "s25fl128s" device entry must be > split into two to match the correct JEDEC ID's for each version. Solves > paging related issues of S25FL128SAGBHI210 chips. > > Signed-off-by: A. Celenk <ahmet.celenk@procenne.com> > > Cc: Boris Brezillon <boris.brezillon@free-electrons.com> > Cc: Marek Vasut <marek.vasut@gmail.com> > --- > drivers/mtd/spi-nor/spi-nor.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c > index 13a5055..1ee2d56 100644 > --- a/drivers/mtd/spi-nor/spi-nor.c > +++ b/drivers/mtd/spi-nor/spi-nor.c > @@ -1898,7 +1898,8 @@ static const struct flash_info spi_nor_ids[] = { > { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) }, > { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) }, > { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) }, > - { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, > + { "s25fl128s0", INFO6(0x012018, 0x4d0080, 256 * 1024, 64, SPI_NOR_QUAD_READ | USE_CLSR) }, > + { "s25fl128s1", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_QUAD_READ | USE_CLSR) }, Why are you dropping the SPI_NOR_DUAL_READ flag in the new entries? > { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, > { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, > { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) }, >
Thanks a lot. I've just pasted what one of the Cypress employee typed. See: https://community.cypress.com/message/183438#183438 I've asked my question with a code snipped from an older kernel. Probably he missed that point and I couldn't notice that flag exist in newer kernels. I'll be adding that flag. On 30.01.2019 14:05, Schrempf Frieder wrote: > On 30.01.19 11:26, A. Celenk wrote: >> Due to two different versions (S25FL128SAGBHI200 and S25FL128SAGBHI210) of >> the s25fl128s qspi memory, the single "s25fl128s" device entry must be >> split into two to match the correct JEDEC ID's for each version. Solves >> paging related issues of S25FL128SAGBHI210 chips. >> >> Signed-off-by: A. Celenk <ahmet.celenk@procenne.com> >> >> Cc: Boris Brezillon <boris.brezillon@free-electrons.com> >> Cc: Marek Vasut <marek.vasut@gmail.com> >> --- >> drivers/mtd/spi-nor/spi-nor.c | 3 ++- >> 1 file changed, 2 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c >> index 13a5055..1ee2d56 100644 >> --- a/drivers/mtd/spi-nor/spi-nor.c >> +++ b/drivers/mtd/spi-nor/spi-nor.c >> @@ -1898,7 +1898,8 @@ static const struct flash_info spi_nor_ids[] = { >> { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) }, >> { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) }, >> { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) }, >> - { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, >> + { "s25fl128s0", INFO6(0x012018, 0x4d0080, 256 * 1024, 64, SPI_NOR_QUAD_READ | USE_CLSR) }, >> + { "s25fl128s1", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_QUAD_READ | USE_CLSR) }, > Why are you dropping the SPI_NOR_DUAL_READ flag in the new entries? > >> { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, >> { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, >> { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 13a5055..1ee2d56 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -1898,7 +1898,8 @@ static const struct flash_info spi_nor_ids[] = { { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) }, { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) }, { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) }, - { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, + { "s25fl128s0", INFO6(0x012018, 0x4d0080, 256 * 1024, 64, SPI_NOR_QUAD_READ | USE_CLSR) }, + { "s25fl128s1", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_QUAD_READ | USE_CLSR) }, { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
Due to two different versions (S25FL128SAGBHI200 and S25FL128SAGBHI210) of the s25fl128s qspi memory, the single "s25fl128s" device entry must be split into two to match the correct JEDEC ID's for each version. Solves paging related issues of S25FL128SAGBHI210 chips. Signed-off-by: A. Celenk <ahmet.celenk@procenne.com> Cc: Boris Brezillon <boris.brezillon@free-electrons.com> Cc: Marek Vasut <marek.vasut@gmail.com> --- drivers/mtd/spi-nor/spi-nor.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)