Message ID | 1546593834-41316-1-git-send-email-ye.li@nxp.com |
---|---|
State | Accepted |
Commit | 9d47d1316da6585bbafe141e42bbdcdfd562bc71 |
Delegated to: | Tom Rini |
Headers | show |
Series | [U-Boot] arm: Round the dma_alloc_coherent memory size to cache line aligned | expand |
On Fri, Jan 04, 2019 at 09:24:14AM +0000, Ye Li wrote: > When running usb dwc3 gadget driver, we meet random USB enumeration failure in fastboot. > The root cause is a cache coherence issue. When it happens, the ctrl_req in > gadget driver is allocated at 0xfe932f40, and the usb_composite_dev (cdev) > is allocated at 0xfe932f60. So after we submit the setup request (cache flushed) to USB > controller, any accessing to usb_composite_dev variable will cause the cache line refill, then > when setup transfer is completed, reading the setup data in ctrl_req will gets old value from > cache not from memory. > > The ctrl_req is allocated by API dma_alloc_coherent, but u-boot don't have cohernet memory. > so it still needs cache maintain operations before/after HW accessing. Since the cache flush or > invalidate bases on cache line, so when the allocated memory size is not cache line aligned, > potentially it may meet such issue. > > This patch modifies the dma_alloc_coherent API to round the size to cache line aligned. > > Signed-off-by: Ye Li <ye.li@nxp.com> > Reviewed-by: Peng Fan <peng.fan@nxp.com> Applied to u-boot/master, thanks!
diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h index 0883b7e..fc5b8f6 100644 --- a/arch/arm/include/asm/dma-mapping.h +++ b/arch/arm/include/asm/dma-mapping.h @@ -13,7 +13,7 @@ static inline void *dma_alloc_coherent(size_t len, unsigned long *handle) { - *handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, len); + *handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, ROUND(len, ARCH_DMA_MINALIGN)); return (void *)*handle; }