| Message ID | 20181203091456.454030-2-tmaimon77@gmail.com |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | SPI-NOR add NPCM FIU controller driver | expand |
On Mon, Dec 03, 2018 at 11:14:55AM +0200, Tomer Maimon wrote: > Added device tree binding documentation for Nuvoton BMC > NPCM Flash Interface Unit(FIU) SPI-NOR controller. > > Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> > --- > Documentation/devicetree/bindings/mtd/npcm-fiu.txt | 64 ++++++++++++++++++++++ > 1 file changed, 64 insertions(+) > create mode 100644 Documentation/devicetree/bindings/mtd/npcm-fiu.txt > > diff --git a/Documentation/devicetree/bindings/mtd/npcm-fiu.txt b/Documentation/devicetree/bindings/mtd/npcm-fiu.txt > new file mode 100644 > index 000000000000..9746cb5b1ced > --- /dev/null > +++ b/Documentation/devicetree/bindings/mtd/npcm-fiu.txt > @@ -0,0 +1,64 @@ > +* Nuvoton FLASH Interface Unit (FIU) SPI Controller > + > +NPCM FIU supports single, dual and quad communication interface. > + > +The NPCM7XX supports three FIU modules, > +FIU0 and FIUx supports two chip selects, > +FIU3 support four chip select. > + > +Required properties: > + - compatible : "nuvoton,npcm750-fiu" for the NPCM7XX BMC > + - #address-cells : should be 1. > + - #size-cells : should be 0. > + - reg : the first contains the register location and length, > + the second contains the memory mapping address and length > + - reg-names: Should contain the reg names "control" and "memory" > + - clocks : phandle of F reference clock. > + > +Required properties in case the pins can be muxed: > + - pinctrl-names : a pinctrl state named "default" must be defined. > + - pinctrl-0 : phandle referencing pin configuration of the device. > + > +Optional property: > + - spix-mode: enable spix-mode for an expansion bus to an ASIC or CPLD. Needs a vendor prefix. Unless this is some standard SPI thing (which I've never heard of). > + > +The SPI device must be a child of the FIU node and must have a > +compatible property as specified in bindings/mtd/jedec,spi-nor.txt > + > +Required property: > +- reg: chip select number. > + > +Optional property: > +- spi-rx-bus-width: see ../spi/spi-bus.txt for the description. > + > +Aliases: > +- All the FIU controller nodes should be represented in the aliases node using > + the following format 'fiu{n}' where n is a unique number for the alias. > + In the NPCM7XX BMC: > + fiu0 represent fiu 0 controller > + fiu1 represent fiu 3 controller > + fiu2 represent fiu x controller Please don't make up your own aliases. Use 'spiX' if anything, but really, why do you need aliases in the first place? > + > +Example: > +fiu3: fiu@c00000000 { spi@... > + compatible = "nuvoton,npcm750-fiu"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0xfb000000 0x1000>, <0x80000000 0x10000000>; > + reg-names = "control", "memory"; > + clocks = <&clk NPCM7XX_CLK_AHB>; > + pinctrl-names = "default"; > + pinctrl-0 = <&spi3_pins>; > + spi-nor@0 { > + compatible = "jedec,spi-nor"; > + spi-rx-bus-width = <2>; > + #address-cells = <1>; > + #size-cells = <1>; > + reg = <0>; > + partition@0 { > + label = "flash_data"; > + reg = <0x0 0x800000>; > + }; > + }; > +}; > + > -- > 2.14.1 >
Hi Rob, Thanks for your comments, The spi-nor drivers are moving to spi (spi-mem), I will make sure to modify the new SPI dt-binding document according your comments once I finish the work on the new SPI driver. https://lkml.org/lkml/2018/12/3/545 Happy new year! Tomer On Wed, 19 Dec 2018 at 17:54, Rob Herring <robh@kernel.org> wrote: > On Mon, Dec 03, 2018 at 11:14:55AM +0200, Tomer Maimon wrote: > > Added device tree binding documentation for Nuvoton BMC > > NPCM Flash Interface Unit(FIU) SPI-NOR controller. > > > > Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> > > --- > > Documentation/devicetree/bindings/mtd/npcm-fiu.txt | 64 > ++++++++++++++++++++++ > > 1 file changed, 64 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/mtd/npcm-fiu.txt > > > > diff --git a/Documentation/devicetree/bindings/mtd/npcm-fiu.txt > b/Documentation/devicetree/bindings/mtd/npcm-fiu.txt > > new file mode 100644 > > index 000000000000..9746cb5b1ced > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/mtd/npcm-fiu.txt > > @@ -0,0 +1,64 @@ > > +* Nuvoton FLASH Interface Unit (FIU) SPI Controller > > + > > +NPCM FIU supports single, dual and quad communication interface. > > + > > +The NPCM7XX supports three FIU modules, > > +FIU0 and FIUx supports two chip selects, > > +FIU3 support four chip select. > > + > > +Required properties: > > + - compatible : "nuvoton,npcm750-fiu" for the NPCM7XX BMC > > + - #address-cells : should be 1. > > + - #size-cells : should be 0. > > + - reg : the first contains the register location and length, > > + the second contains the memory mapping address and length > > + - reg-names: Should contain the reg names "control" and "memory" > > + - clocks : phandle of F reference clock. > > + > > +Required properties in case the pins can be muxed: > > + - pinctrl-names : a pinctrl state named "default" must be defined. > > + - pinctrl-0 : phandle referencing pin configuration of the device. > > + > > +Optional property: > > + - spix-mode: enable spix-mode for an expansion bus to an ASIC or CPLD. > > Needs a vendor prefix. Unless this is some standard SPI thing (which > I've never heard of). > > > + > > +The SPI device must be a child of the FIU node and must have a > > +compatible property as specified in bindings/mtd/jedec,spi-nor.txt > > + > > +Required property: > > +- reg: chip select number. > > + > > +Optional property: > > +- spi-rx-bus-width: see ../spi/spi-bus.txt for the description. > > + > > +Aliases: > > +- All the FIU controller nodes should be represented in the aliases > node using > > + the following format 'fiu{n}' where n is a unique number for the > alias. > > + In the NPCM7XX BMC: > > + fiu0 represent fiu 0 controller > > + fiu1 represent fiu 3 controller > > + fiu2 represent fiu x controller > > Please don't make up your own aliases. Use 'spiX' if anything, but > really, why do you need aliases in the first place? > > > + > > +Example: > > +fiu3: fiu@c00000000 { > > spi@... > > > + compatible = "nuvoton,npcm750-fiu"; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + reg = <0xfb000000 0x1000>, <0x80000000 0x10000000>; > > + reg-names = "control", "memory"; > > + clocks = <&clk NPCM7XX_CLK_AHB>; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&spi3_pins>; > > + spi-nor@0 { > > + compatible = "jedec,spi-nor"; > > + spi-rx-bus-width = <2>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + reg = <0>; > > + partition@0 { > > + label = "flash_data"; > > + reg = <0x0 0x800000>; > > + }; > > + }; > > +}; > > + > > -- > > 2.14.1 > > > <div dir="ltr"><div dir="ltr">Hi Rob,<div><br></div><div>Thanks for your comments,</div><div><br></div><div>The spi-nor drivers are moving to spi (spi-mem), I will make sure to modify the new SPI dt-binding document according your comments once I finish the work on the new SPI driver.</div><div><br></div><div><a href="https://lkml.org/lkml/2018/12/3/545">https://lkml.org/lkml/2018/12/3/545</a><br></div><div><br></div><div>Happy new year!</div><div><br></div><div>Tomer</div></div></div><br><div class="gmail_quote"><div dir="ltr">On Wed, 19 Dec 2018 at 17:54, Rob Herring <<a href="mailto:robh@kernel.org">robh@kernel.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">On Mon, Dec 03, 2018 at 11:14:55AM +0200, Tomer Maimon wrote:<br> > Added device tree binding documentation for Nuvoton BMC<br> > NPCM Flash Interface Unit(FIU) SPI-NOR controller.<br> > <br> > Signed-off-by: Tomer Maimon <<a href="mailto:tmaimon77@gmail.com" target="_blank">tmaimon77@gmail.com</a>><br> > ---<br> > Documentation/devicetree/bindings/mtd/npcm-fiu.txt | 64 ++++++++++++++++++++++<br> > 1 file changed, 64 insertions(+)<br> > create mode 100644 Documentation/devicetree/bindings/mtd/npcm-fiu.txt<br> > <br> > diff --git a/Documentation/devicetree/bindings/mtd/npcm-fiu.txt b/Documentation/devicetree/bindings/mtd/npcm-fiu.txt<br> > new file mode 100644<br> > index 000000000000..9746cb5b1ced<br> > --- /dev/null<br> > +++ b/Documentation/devicetree/bindings/mtd/npcm-fiu.txt<br> > @@ -0,0 +1,64 @@<br> > +* Nuvoton FLASH Interface Unit (FIU) SPI Controller<br> > +<br> > +NPCM FIU supports single, dual and quad communication interface.<br> > +<br> > +The NPCM7XX supports three FIU modules,<br> > +FIU0 and FIUx supports two chip selects,<br> > +FIU3 support four chip select.<br> > +<br> > +Required properties:<br> > + - compatible : "nuvoton,npcm750-fiu" for the NPCM7XX BMC<br> > + - #address-cells : should be 1.<br> > + - #size-cells : should be 0.<br> > + - reg : the first contains the register location and length,<br> > + the second contains the memory mapping address and length<br> > + - reg-names: Should contain the reg names "control" and "memory"<br> > + - clocks : phandle of F reference clock.<br> > +<br> > +Required properties in case the pins can be muxed:<br> > + - pinctrl-names : a pinctrl state named "default" must be defined.<br> > + - pinctrl-0 : phandle referencing pin configuration of the device.<br> > +<br> > +Optional property:<br> > + - spix-mode: enable spix-mode for an expansion bus to an ASIC or CPLD.<br> <br> Needs a vendor prefix. Unless this is some standard SPI thing (which <br> I've never heard of).<br> <br> > +<br> > +The SPI device must be a child of the FIU node and must have a<br> > +compatible property as specified in bindings/mtd/jedec,spi-nor.txt<br> > +<br> > +Required property:<br> > +- reg: chip select number.<br> > +<br> > +Optional property:<br> > +- spi-rx-bus-width: see ../spi/spi-bus.txt for the description.<br> > +<br> > +Aliases:<br> > +- All the FIU controller nodes should be represented in the aliases node using<br> > + the following format 'fiu{n}' where n is a unique number for the alias.<br> > + In the NPCM7XX BMC:<br> > + fiu0 represent fiu 0 controller<br> > + fiu1 represent fiu 3 controller<br> > + fiu2 represent fiu x controller<br> <br> Please don't make up your own aliases. Use 'spiX' if anything, but <br> really, why do you need aliases in the first place?<br> <br> > +<br> > +Example:<br> > +fiu3: fiu@c00000000 {<br> <br> spi@...<br> <br> > + compatible = "nuvoton,npcm750-fiu";<br> > + #address-cells = <1>;<br> > + #size-cells = <0>;<br> > + reg = <0xfb000000 0x1000>, <0x80000000 0x10000000>;<br> > + reg-names = "control", "memory";<br> > + clocks = <&clk NPCM7XX_CLK_AHB>;<br> > + pinctrl-names = "default";<br> > + pinctrl-0 = <&spi3_pins>;<br> > + spi-nor@0 {<br> > + compatible = "jedec,spi-nor";<br> > + spi-rx-bus-width = <2>;<br> > + #address-cells = <1>;<br> > + #size-cells = <1>;<br> > + reg = <0>;<br> > + partition@0 {<br> > + label = "flash_data";<br> > + reg = <0x0 0x800000>;<br> > + };<br> > + };<br> > +};<br> > +<br> > -- <br> > 2.14.1<br> > <br> </blockquote></div>
diff --git a/Documentation/devicetree/bindings/mtd/npcm-fiu.txt b/Documentation/devicetree/bindings/mtd/npcm-fiu.txt new file mode 100644 index 000000000000..9746cb5b1ced --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/npcm-fiu.txt @@ -0,0 +1,64 @@ +* Nuvoton FLASH Interface Unit (FIU) SPI Controller + +NPCM FIU supports single, dual and quad communication interface. + +The NPCM7XX supports three FIU modules, +FIU0 and FIUx supports two chip selects, +FIU3 support four chip select. + +Required properties: + - compatible : "nuvoton,npcm750-fiu" for the NPCM7XX BMC + - #address-cells : should be 1. + - #size-cells : should be 0. + - reg : the first contains the register location and length, + the second contains the memory mapping address and length + - reg-names: Should contain the reg names "control" and "memory" + - clocks : phandle of F reference clock. + +Required properties in case the pins can be muxed: + - pinctrl-names : a pinctrl state named "default" must be defined. + - pinctrl-0 : phandle referencing pin configuration of the device. + +Optional property: + - spix-mode: enable spix-mode for an expansion bus to an ASIC or CPLD. + +The SPI device must be a child of the FIU node and must have a +compatible property as specified in bindings/mtd/jedec,spi-nor.txt + +Required property: +- reg: chip select number. + +Optional property: +- spi-rx-bus-width: see ../spi/spi-bus.txt for the description. + +Aliases: +- All the FIU controller nodes should be represented in the aliases node using + the following format 'fiu{n}' where n is a unique number for the alias. + In the NPCM7XX BMC: + fiu0 represent fiu 0 controller + fiu1 represent fiu 3 controller + fiu2 represent fiu x controller + +Example: +fiu3: fiu@c00000000 { + compatible = "nuvoton,npcm750-fiu"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfb000000 0x1000>, <0x80000000 0x10000000>; + reg-names = "control", "memory"; + clocks = <&clk NPCM7XX_CLK_AHB>; + pinctrl-names = "default"; + pinctrl-0 = <&spi3_pins>; + spi-nor@0 { + compatible = "jedec,spi-nor"; + spi-rx-bus-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + partition@0 { + label = "flash_data"; + reg = <0x0 0x800000>; + }; + }; +}; +
Added device tree binding documentation for Nuvoton BMC NPCM Flash Interface Unit(FIU) SPI-NOR controller. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> --- Documentation/devicetree/bindings/mtd/npcm-fiu.txt | 64 ++++++++++++++++++++++ 1 file changed, 64 insertions(+) create mode 100644 Documentation/devicetree/bindings/mtd/npcm-fiu.txt