| Message ID | 20181009112837.2517-1-peron.clem@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | ARM: debug: enable UART1 for socfpga Cyclone5 | expand |
Hi Clément, On 10/09/2018 06:28 AM, Clément Péron wrote: > Cyclone5 and Arria10 doesn't have the same memory map for UART1. > > Split the SOCFPGA_UART1 into 2 options to allow debugging on UART1 for Cylone5. > I'm not sure the need for this patch. Are there any cyclone5 based boards that has UART1 as the debug uart? I see that all of them are using UART0. Dinh
HI Dinh, On Tue, 23 Oct 2018 at 16:04, Dinh Nguyen <dinguyen@kernel.org> wrote: > > Hi Clément, > > On 10/09/2018 06:28 AM, Clément Péron wrote: > > Cyclone5 and Arria10 doesn't have the same memory map for UART1. > > > > Split the SOCFPGA_UART1 into 2 options to allow debugging on UART1 for Cylone5. > > > > I'm not sure the need for this patch. Are there any cyclone5 based > boards that has UART1 as the debug uart? I see that all of them are > using UART0. There is no upstream device with this UART used. But the board I have use it, and there is no limitation to not have it available upstream no ? Thanks, Clement > > Dinh >
On 10/23/2018 09:44 AM, Clément Péron wrote: > HI Dinh, > > On Tue, 23 Oct 2018 at 16:04, Dinh Nguyen <dinguyen@kernel.org> wrote: >> >> Hi Clément, >> >> On 10/09/2018 06:28 AM, Clément Péron wrote: >>> Cyclone5 and Arria10 doesn't have the same memory map for UART1. >>> >>> Split the SOCFPGA_UART1 into 2 options to allow debugging on UART1 for Cylone5. >>> >> >> I'm not sure the need for this patch. Are there any cyclone5 based >> boards that has UART1 as the debug uart? I see that all of them are >> using UART0. > > There is no upstream device with this UART used. But the board I have > use it, and there is no limitation to not have it available upstream > no ? > I see. Then I don't think the patch is applicable because none of the upstream devices need it. Now, if you were to upstream your board that uses UART1, then there will be a case for this patch. Do you agree? Dinh
On Tue, Oct 23, 2018 at 03:35:31PM -0500, Dinh Nguyen wrote: > > > On 10/23/2018 09:44 AM, Clément Péron wrote: > > HI Dinh, > > > > On Tue, 23 Oct 2018 at 16:04, Dinh Nguyen <dinguyen@kernel.org> wrote: > >> > >> Hi Clément, > >> > >> On 10/09/2018 06:28 AM, Clément Péron wrote: > >>> Cyclone5 and Arria10 doesn't have the same memory map for UART1. > >>> > >>> Split the SOCFPGA_UART1 into 2 options to allow debugging on UART1 for Cylone5. > >>> > >> > >> I'm not sure the need for this patch. Are there any cyclone5 based > >> boards that has UART1 as the debug uart? I see that all of them are > >> using UART0. > > > > There is no upstream device with this UART used. But the board I have > > use it, and there is no limitation to not have it available upstream > > no ? > > > > I see. Then I don't think the patch is applicable because none of the > upstream devices need it. Now, if you were to upstream your board that > uses UART1, then there will be a case for this patch. Do you agree? I'd not say having to upstream the board is a sensible precondition for such a patch. One of the arguments for moving ARM to dt was that this allows to separate the machine specifics from the code. So I'd say if Clément has a need, this is a good enough reason to take this patch. Just my 0.02 €, Uwe
Hi, On Wed, 24 Oct 2018 at 08:51, Uwe Kleine-König <u.kleine-koenig@pengutronix.de> wrote: > > On Tue, Oct 23, 2018 at 03:35:31PM -0500, Dinh Nguyen wrote: > > > > > > On 10/23/2018 09:44 AM, Clément Péron wrote: > > > HI Dinh, > > > > > > On Tue, 23 Oct 2018 at 16:04, Dinh Nguyen <dinguyen@kernel.org> wrote: > > >> > > >> Hi Clément, > > >> > > >> On 10/09/2018 06:28 AM, Clément Péron wrote: > > >>> Cyclone5 and Arria10 doesn't have the same memory map for UART1. > > >>> > > >>> Split the SOCFPGA_UART1 into 2 options to allow debugging on UART1 for Cylone5. > > >>> > > >> > > >> I'm not sure the need for this patch. Are there any cyclone5 based > > >> boards that has UART1 as the debug uart? I see that all of them are > > >> using UART0. > > > > > > There is no upstream device with this UART used. But the board I have > > > use it, and there is no limitation to not have it available upstream > > > no ? > > > > > > > I see. Then I don't think the patch is applicable because none of the > > upstream devices need it. Now, if you were to upstream your board that > > uses UART1, then there will be a case for this patch. Do you agree? I don't think my board is upstreamable it's not a devkit and not really interesting for the community. It's really a trivial patch and it will avoid wasting time to another owner of CycloneV board who would like to have debug on UART1 Thanks Clement > > I'd not say having to upstream the board is a sensible precondition for > such a patch. One of the arguments for moving ARM to dt was that this > allows to separate the machine specifics from the code. So I'd say if > Clément has a need, this is a good enough reason to take this patch. > > Just my 0.02 €, > Uwe > > -- > Pengutronix e.K. | Uwe Kleine-König | > Industrial Linux Solutions | http://www.pengutronix.de/ |
Hi On 10/24/2018 09:11 AM, Clément Péron wrote: > Hi, > > On Wed, 24 Oct 2018 at 08:51, Uwe Kleine-König > <u.kleine-koenig@pengutronix.de> wrote: >> >> On Tue, Oct 23, 2018 at 03:35:31PM -0500, Dinh Nguyen wrote: >>> >>> >>> On 10/23/2018 09:44 AM, Clément Péron wrote: >>>> HI Dinh, >>>> >>>> On Tue, 23 Oct 2018 at 16:04, Dinh Nguyen <dinguyen@kernel.org> wrote: >>>>> >>>>> Hi Clément, >>>>> >>>>> On 10/09/2018 06:28 AM, Clément Péron wrote: >>>>>> Cyclone5 and Arria10 doesn't have the same memory map for UART1. >>>>>> >>>>>> Split the SOCFPGA_UART1 into 2 options to allow debugging on UART1 for Cylone5. >>>>>> >>>>> >>>>> I'm not sure the need for this patch. Are there any cyclone5 based >>>>> boards that has UART1 as the debug uart? I see that all of them are >>>>> using UART0. >>>> >>>> There is no upstream device with this UART used. But the board I have >>>> use it, and there is no limitation to not have it available upstream >>>> no ? >>>> >>> >>> I see. Then I don't think the patch is applicable because none of the >>> upstream devices need it. Now, if you were to upstream your board that >>> uses UART1, then there will be a case for this patch. Do you agree? > > I don't think my board is upstreamable it's not a devkit and not > really interesting for the community. > > It's really a trivial patch and it will avoid wasting time to another > owner of CycloneV board who would like to have debug on UART1 > I'll apply this after the merge window. Thanks, Dinh
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index f6fcb8a79889..25ebdcefe403 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -1079,14 +1079,21 @@ choice Say Y here if you want kernel low-level debugging support on SOCFPGA(Cyclone 5 and Arria 5) based platforms. - config DEBUG_SOCFPGA_UART1 + config DEBUG_SOCFPGA_ARRIA10_UART1 depends on ARCH_SOCFPGA - bool "Use SOCFPGA UART1 for low-level debug" + bool "Use SOCFPGA Arria10 UART1 for low-level debug" select DEBUG_UART_8250 help Say Y here if you want kernel low-level debugging support on SOCFPGA(Arria 10) based platforms. + config DEBUG_SOCFPGA_CYCLONE5_UART1 + depends on ARCH_SOCFPGA + bool "Use SOCFPGA Cyclone 5 UART1 for low-level debug" + select DEBUG_UART_8250 + help + Say Y here if you want kernel low-level debugging support + on SOCFPGA(Cyclone 5 and Arria 5) based platforms. config DEBUG_SUN9I_UART0 bool "Kernel low-level debugging messages via sun9i UART0" @@ -1647,7 +1654,8 @@ config DEBUG_UART_PHYS default 0xfe800000 if ARCH_IOP32X default 0xff690000 if DEBUG_RK32_UART2 default 0xffc02000 if DEBUG_SOCFPGA_UART0 - default 0xffc02100 if DEBUG_SOCFPGA_UART1 + default 0xffc02100 if DEBUG_SOCFPGA_ARRIA10_UART1 + default 0xffc03000 if DEBUG_SOCFPGA_CYCLONE5_UART1 default 0xffd82340 if ARCH_IOP13XX default 0xffe40000 if DEBUG_RCAR_GEN1_SCIF0 default 0xffe42000 if DEBUG_RCAR_GEN1_SCIF2 @@ -1754,7 +1762,8 @@ config DEBUG_UART_VIRT default 0xfeb30c00 if DEBUG_KEYSTONE_UART0 default 0xfeb31000 if DEBUG_KEYSTONE_UART1 default 0xfec02000 if DEBUG_SOCFPGA_UART0 - default 0xfec02100 if DEBUG_SOCFPGA_UART1 + default 0xfec02100 if DEBUG_SOCFPGA_ARRIA10_UART1 + default 0xfec03000 if DEBUG_SOCFPGA_CYCLONE5_UART1 default 0xfec12000 if (DEBUG_MVEBU_UART0 || DEBUG_MVEBU_UART0_ALTERNATE) && ARCH_MVEBU default 0xfec12100 if DEBUG_MVEBU_UART1_ALTERNATE default 0xfec10000 if DEBUG_SIRFATLAS7_UART0 @@ -1803,9 +1812,9 @@ config DEBUG_UART_8250_WORD depends on DEBUG_LL_UART_8250 || DEBUG_UART_8250 depends on DEBUG_UART_8250_SHIFT >= 2 default y if DEBUG_PICOXCELL_UART || \ - DEBUG_SOCFPGA_UART0 || DEBUG_SOCFPGA_UART1 || \ - DEBUG_KEYSTONE_UART0 || DEBUG_KEYSTONE_UART1 || \ - DEBUG_ALPINE_UART0 || \ + DEBUG_SOCFPGA_UART0 || DEBUG_SOCFPGA_ARRIA10_UART1 || \ + DEBUG_SOCFPGA_CYCLONE5_UART1 || DEBUG_KEYSTONE_UART0 || \ + DEBUG_KEYSTONE_UART1 || DEBUG_ALPINE_UART0 || \ DEBUG_DAVINCI_DMx_UART0 || DEBUG_DAVINCI_DA8XX_UART1 || \ DEBUG_DAVINCI_DA8XX_UART2 || DEBUG_BCM_IPROC_UART3 || \ DEBUG_BCM_KONA_UART || DEBUG_RK32_UART2
Cyclone5 and Arria10 doesn't have the same memory map for UART1. Split the SOCFPGA_UART1 into 2 options to allow debugging on UART1 for Cylone5. Signed-off-by: Clément Péron <peron.clem@gmail.com> --- arch/arm/Kconfig.debug | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-)