| Message ID | 1298398783-18771-1-git-send-email-peter.maydell@linaro.org |
|---|---|
| State | New |
| Headers | show |
On 22 February 2011 18:19, Peter Maydell <peter.maydell@linaro.org> wrote: > + tmp = tcg_const_i32(0); > + store_reg(s, rt, tmp); This generates spurious "resource leak" warnings, because store_reg() calls dead_tmp() so you can't store anything you didn't get from new_tmp(). I think I'll do what Aurelien suggested and put together a patch that implements the resource-leak debug as a proper facility at the tcg level. -- PMM
On Tue, Feb 22, 2011 at 06:19:43PM +0000, Peter Maydell wrote: > Newer ARM kernels try to probe for whether the CPU has hardware breakpoint > support. For this to work QEMU has to implement a minimal set of the cp14 > debug registers. The architecture requires v7 cores to implement debug > and so there is no defined way to report its absence; however in practice > returning a zero DBGDIDR (ie with a reserved value for "debug architecture > version") should cause well-written hw debug users to do the right thing. > We also implement DBGDRAR and DBGDSAR as RAZ, indicating no memory mapped > debug components. > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> > --- > target-arm/translate.c | 28 ++++++++++++++++++++++++++++ > 1 files changed, 28 insertions(+), 0 deletions(-) Thanks, applied. > diff --git a/target-arm/translate.c b/target-arm/translate.c > index dbd958b..d05859d 100644 > --- a/target-arm/translate.c > +++ b/target-arm/translate.c > @@ -5769,6 +5769,34 @@ static int disas_cp14_read(CPUState * env, DisasContext *s, uint32_t insn) > int rt = (insn >> 12) & 0xf; > TCGv tmp; > > + /* Minimal set of debug registers, since we don't support debug */ > + if (op1 == 0 && crn == 0 && op2 == 0) { > + switch (crm) { > + case 0: > + /* DBGDIDR: just RAZ. In particular this means the > + * "debug architecture version" bits will read as > + * a reserved value, which should cause Linux to > + * not try to use the debug hardware. > + */ > + tmp = tcg_const_i32(0); > + store_reg(s, rt, tmp); > + return 0; > + case 1: > + case 2: > + /* DBGDRAR and DBGDSAR: v7 only. Always RAZ since we > + * don't implement memory mapped debug components > + */ > + if (ENABLE_ARCH_7) { > + tmp = tcg_const_i32(0); > + store_reg(s, rt, tmp); > + return 0; > + } > + break; > + default: > + break; > + } > + } > + > if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { > if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) { > /* TEECR */ > -- > 1.7.1 > > >
diff --git a/target-arm/translate.c b/target-arm/translate.c index dbd958b..d05859d 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -5769,6 +5769,34 @@ static int disas_cp14_read(CPUState * env, DisasContext *s, uint32_t insn) int rt = (insn >> 12) & 0xf; TCGv tmp; + /* Minimal set of debug registers, since we don't support debug */ + if (op1 == 0 && crn == 0 && op2 == 0) { + switch (crm) { + case 0: + /* DBGDIDR: just RAZ. In particular this means the + * "debug architecture version" bits will read as + * a reserved value, which should cause Linux to + * not try to use the debug hardware. + */ + tmp = tcg_const_i32(0); + store_reg(s, rt, tmp); + return 0; + case 1: + case 2: + /* DBGDRAR and DBGDSAR: v7 only. Always RAZ since we + * don't implement memory mapped debug components + */ + if (ENABLE_ARCH_7) { + tmp = tcg_const_i32(0); + store_reg(s, rt, tmp); + return 0; + } + break; + default: + break; + } + } + if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) { /* TEECR */
Newer ARM kernels try to probe for whether the CPU has hardware breakpoint support. For this to work QEMU has to implement a minimal set of the cp14 debug registers. The architecture requires v7 cores to implement debug and so there is no defined way to report its absence; however in practice returning a zero DBGDIDR (ie with a reserved value for "debug architecture version") should cause well-written hw debug users to do the right thing. We also implement DBGDRAR and DBGDSAR as RAZ, indicating no memory mapped debug components. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target-arm/translate.c | 28 ++++++++++++++++++++++++++++ 1 files changed, 28 insertions(+), 0 deletions(-)