diff mbox series

powerpc/powernv: Add support for NPU2 relaxed-ordering mode

Message ID 1533698243-25972-1-git-send-email-arbab@linux.ibm.com (mailing list archive)
State Changes Requested
Headers show
Series powerpc/powernv: Add support for NPU2 relaxed-ordering mode | expand

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Commit Message

Reza Arbab Aug. 8, 2018, 3:17 a.m. UTC 
From: Alistair Popple <alistair@popple.id.au>

Some device drivers support out of order access to GPU memory. This does
not affect the CPU view of memory but it does affect the GPU view, so it
should only be enabled once the GPU driver has requested it. Add APIs
allowing a driver to do so.

Signed-off-by: Alistair Popple <alistair@popple.id.au>
[arbab@linux.ibm.com: Rebase, add commit log]
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
---
 arch/powerpc/include/asm/opal-api.h            |  4 ++-
 arch/powerpc/include/asm/opal.h                |  3 ++
 arch/powerpc/include/asm/powernv.h             | 12 ++++++++
 arch/powerpc/platforms/powernv/npu-dma.c       | 39 ++++++++++++++++++++++++++
 arch/powerpc/platforms/powernv/opal-wrappers.S |  2 ++
 5 files changed, 59 insertions(+), 1 deletion(-)

Comments

Michael Ellerman Aug. 10, 2018, 7:07 a.m. UTC | #1 
Reza Arbab <arbab@linux.ibm.com> writes:
> From: Alistair Popple <alistair@popple.id.au>
>
> Some device drivers support out of order access to GPU memory. This does
> not affect the CPU view of memory but it does affect the GPU view, so it
> should only be enabled once the GPU driver has requested it. Add APIs
> allowing a driver to do so.

Do we have any indication which drivers we are expecting to use this?

I'd prefer not to merge a new API unless we at least have some idea
what's going to use it.

cheers
Alistair Popple Aug. 10, 2018, 8:07 a.m. UTC | #2 
On Friday, 10 August 2018 5:07:56 PM AEST Michael Ellerman wrote:
> Reza Arbab <arbab@linux.ibm.com> writes:
> > From: Alistair Popple <alistair@popple.id.au>
> >
> > Some device drivers support out of order access to GPU memory. This does
> > not affect the CPU view of memory but it does affect the GPU view, so it
> > should only be enabled once the GPU driver has requested it. Add APIs
> > allowing a driver to do so.
> 
> Do we have any indication which drivers we are expecting to use this?

I believe there is an internal driver that required these but I'm not sure if
there were any plans to make these available upstream or not.

> I'd prefer not to merge a new API unless we at least have some idea
> what's going to use it.

Fair enough. Unfortunately I am not aware of users future plans for usage of
this API.

- Alistair

> cheers
>
diff mbox series

Patch

diff --git a/arch/powerpc/include/asm/opal-api.h b/arch/powerpc/include/asm/opal-api.h
index 3bab299..be6fe23e 100644
--- a/arch/powerpc/include/asm/opal-api.h
+++ b/arch/powerpc/include/asm/opal-api.h
@@ -208,7 +208,9 @@ 
 #define OPAL_SENSOR_READ_U64			162
 #define OPAL_PCI_GET_PBCQ_TUNNEL_BAR		164
 #define OPAL_PCI_SET_PBCQ_TUNNEL_BAR		165
-#define OPAL_LAST				165
+#define OPAL_NPU_SET_RELAXED_ORDER		168
+#define OPAL_NPU_GET_RELAXED_ORDER		169
+#define OPAL_LAST				169
 
 #define QUIESCE_HOLD			1 /* Spin all calls at entry */
 #define QUIESCE_REJECT			2 /* Fail all calls with OPAL_BUSY */
diff --git a/arch/powerpc/include/asm/opal.h b/arch/powerpc/include/asm/opal.h
index e1b2910..48bea30 100644
--- a/arch/powerpc/include/asm/opal.h
+++ b/arch/powerpc/include/asm/opal.h
@@ -43,6 +43,9 @@  int64_t opal_npu_spa_clear_cache(uint64_t phb_id, uint32_t bdfn,
 				uint64_t PE_handle);
 int64_t opal_npu_tl_set(uint64_t phb_id, uint32_t bdfn, long cap,
 			uint64_t rate_phys, uint32_t size);
+int64_t opal_npu_set_relaxed_order(uint64_t phb_id, uint16_t bdfn,
+				   bool request_enabled);
+int64_t opal_npu_get_relaxed_order(uint64_t phb_id, uint16_t bdfn);
 int64_t opal_console_write(int64_t term_number, __be64 *length,
 			   const uint8_t *buffer);
 int64_t opal_console_read(int64_t term_number, __be64 *length,
diff --git a/arch/powerpc/include/asm/powernv.h b/arch/powerpc/include/asm/powernv.h
index 2f3ff7a..874ec6d 100644
--- a/arch/powerpc/include/asm/powernv.h
+++ b/arch/powerpc/include/asm/powernv.h
@@ -22,6 +22,8 @@  extern void pnv_npu2_destroy_context(struct npu_context *context,
 extern int pnv_npu2_handle_fault(struct npu_context *context, uintptr_t *ea,
 				unsigned long *flags, unsigned long *status,
 				int count);
+int pnv_npu2_request_relaxed_ordering(struct pci_dev *pdev, bool enable);
+int pnv_npu2_get_relaxed_ordering(struct pci_dev *pdev);
 
 void pnv_tm_init(void);
 #else
@@ -39,6 +41,16 @@  static inline int pnv_npu2_handle_fault(struct npu_context *context,
 	return -ENODEV;
 }
 
+static int pnv_npu2_request_relaxed_ordering(struct pci_dev *pdev, bool enable)
+{
+	return -ENODEV;
+}
+
+static int pnv_npu2_get_relaxed_ordering(struct pci_dev *pdev)
+{
+	return -ENODEV;
+}
+
 static inline void pnv_tm_init(void) { }
 static inline void pnv_power9_force_smt4(void) { }
 #endif
diff --git a/arch/powerpc/platforms/powernv/npu-dma.c b/arch/powerpc/platforms/powernv/npu-dma.c
index 8cdf91f..038dc1e 100644
--- a/arch/powerpc/platforms/powernv/npu-dma.c
+++ b/arch/powerpc/platforms/powernv/npu-dma.c
@@ -27,6 +27,7 @@ 
 #include <asm/pnv-pci.h>
 #include <asm/msi_bitmap.h>
 #include <asm/opal.h>
+#include <asm/ppc-pci.h>
 
 #include "powernv.h"
 #include "pci.h"
@@ -988,3 +989,41 @@  int pnv_npu2_init(struct pnv_phb *phb)
 
 	return 0;
 }
+
+/*
+ * Request relaxed ordering be enabled or disabled for the given PCI device.
+ * This function may or may not actually enable relaxed ordering depending on
+ * the exact system configuration. Use pnv_npu2_get_relaxed_ordering() below to
+ * determine the current state of relaxed ordering.
+ */
+int pnv_npu2_request_relaxed_ordering(struct pci_dev *pdev, bool enable)
+{
+	struct pci_controller *hose;
+	struct pnv_phb *phb;
+	int rc;
+
+	hose = pci_bus_to_host(pdev->bus);
+	phb = hose->private_data;
+
+	rc = opal_npu_set_relaxed_order(phb->opal_id,
+				PCI_DEVID(pdev->bus->number, pdev->devfn),
+				enable);
+	if (rc != OPAL_SUCCESS && rc != OPAL_CONSTRAINED)
+		return -EPERM;
+
+	return 0;
+}
+EXPORT_SYMBOL(pnv_npu2_request_relaxed_ordering);
+
+int pnv_npu2_get_relaxed_ordering(struct pci_dev *pdev)
+{
+	struct pci_controller *hose;
+	struct pnv_phb *phb;
+
+	hose = pci_bus_to_host(pdev->bus);
+	phb = hose->private_data;
+
+	return opal_npu_get_relaxed_order(phb->opal_id,
+				PCI_DEVID(pdev->bus->number, pdev->devfn));
+}
+EXPORT_SYMBOL(pnv_npu2_get_relaxed_ordering);
diff --git a/arch/powerpc/platforms/powernv/opal-wrappers.S b/arch/powerpc/platforms/powernv/opal-wrappers.S
index a8d9b40..3c72faf 100644
--- a/arch/powerpc/platforms/powernv/opal-wrappers.S
+++ b/arch/powerpc/platforms/powernv/opal-wrappers.S
@@ -327,3 +327,5 @@  OPAL_CALL(opal_npu_tl_set,			OPAL_NPU_TL_SET);
 OPAL_CALL(opal_pci_get_pbcq_tunnel_bar,		OPAL_PCI_GET_PBCQ_TUNNEL_BAR);
 OPAL_CALL(opal_pci_set_pbcq_tunnel_bar,		OPAL_PCI_SET_PBCQ_TUNNEL_BAR);
 OPAL_CALL(opal_sensor_read_u64,			OPAL_SENSOR_READ_U64);
+OPAL_CALL(opal_npu_set_relaxed_order,		OPAL_NPU_SET_RELAXED_ORDER);
+OPAL_CALL(opal_npu_get_relaxed_order,		OPAL_NPU_GET_RELAXED_ORDER);