| Message ID | 1296856680-28840-1-git-send-email-yorksun@freescale.com |
|---|---|
| State | Accepted |
| Commit | dea8bd627c26bb2d17d7079b374352301af4a028 |
| Delegated to: | Kumar Gala |
| Headers | show |
On Feb 4, 2011, at 3:57 PM, York Sun wrote: > Most of time U-boot doesn't get an exact clock number. For example, clock > 900MHz may be detected as 899.99MHz. 800MHz could be 799.99MHz. Update the > table to align the desired clocks in the middle. > > Signed-off-by: York Sun <yorksun@freescale.com> > --- > board/freescale/corenet_ds/p4080ds_ddr.c | 16 ++++++++-------- > 1 files changed, 8 insertions(+), 8 deletions(-) applied to 85xx next - k
diff --git a/board/freescale/corenet_ds/p4080ds_ddr.c b/board/freescale/corenet_ds/p4080ds_ddr.c index ccb9da8..844e1d7 100644 --- a/board/freescale/corenet_ds/p4080ds_ddr.c +++ b/board/freescale/corenet_ds/p4080ds_ddr.c @@ -334,17 +334,17 @@ fsl_ddr_cfg_regs_t ddr_cfg_regs_1200_2nd = { }; fixed_ddr_parm_t fixed_ddr_parm_0[] = { - {800, 900, &ddr_cfg_regs_800}, - {900, 1000, &ddr_cfg_regs_900}, - {1000, 1200, &ddr_cfg_regs_1000}, - {1200, 1300, &ddr_cfg_regs_1200}, + {750, 850, &ddr_cfg_regs_800}, + {850, 950, &ddr_cfg_regs_900}, + {950, 1050, &ddr_cfg_regs_1000}, + {1050, 1250, &ddr_cfg_regs_1200}, {0, 0, NULL} }; fixed_ddr_parm_t fixed_ddr_parm_1[] = { - {800, 900, &ddr_cfg_regs_800_2nd}, - {900, 1000, &ddr_cfg_regs_900_2nd}, - {1000, 1200, &ddr_cfg_regs_1000_2nd}, - {1200, 1300, &ddr_cfg_regs_1200_2nd}, + {750, 850, &ddr_cfg_regs_800_2nd}, + {850, 950, &ddr_cfg_regs_900_2nd}, + {950, 1050, &ddr_cfg_regs_1000_2nd}, + {1050, 1250, &ddr_cfg_regs_1200_2nd}, {0, 0, NULL} };
Most of time U-boot doesn't get an exact clock number. For example, clock 900MHz may be detected as 899.99MHz. 800MHz could be 799.99MHz. Update the table to align the desired clocks in the middle. Signed-off-by: York Sun <yorksun@freescale.com> --- board/freescale/corenet_ds/p4080ds_ddr.c | 16 ++++++++-------- 1 files changed, 8 insertions(+), 8 deletions(-)