| Message ID | 20180712154152.32183-3-peter.maydell@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | a couple of GICv2 bug fixes | expand |
On 07/12/2018 10:41 AM, Peter Maydell wrote: > The GICD_ITARGETSR implementation still has some 11MPCore behaviour > that we were incorrectly using in our GICv1 and GICv2 implementations > for the case where the interrupt number is less than GIC_INTERNAL. > The desired behaviour here is: > * for 11MPCore: RAZ/WI for irqs 0..28; read a number matching the > CPU doing the read for irqs 29..31 > * for GICv1 and v2: RAZ/WI if uniprocessor; otherwise read a > number matching the CPU doing the read for all irqs < 32 > > Stop squashing GICD_ITARGETSR to 0 for IRQs 0..28 unless this > is an 11MPCore GIC. > > Reported-by: Jan Kiszka <jan.kiszka@web.de> > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> > --- > hw/intc/arm_gic.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
On 07/12/2018 05:41 PM, Peter Maydell wrote: > The GICD_ITARGETSR implementation still has some 11MPCore behaviour > that we were incorrectly using in our GICv1 and GICv2 implementations > for the case where the interrupt number is less than GIC_INTERNAL. > The desired behaviour here is: > * for 11MPCore: RAZ/WI for irqs 0..28; read a number matching the > CPU doing the read for irqs 29..31 > * for GICv1 and v2: RAZ/WI if uniprocessor; otherwise read a > number matching the CPU doing the read for all irqs < 32 > > Stop squashing GICD_ITARGETSR to 0 for IRQs 0..28 unless this > is an 11MPCore GIC. > > Reported-by: Jan Kiszka <jan.kiszka@web.de> > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> > --- > hw/intc/arm_gic.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) Reviewed-by: Luc Michel <luc.michel@greensocs.com>
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index b0a69d6386e..34dc84ae813 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -751,7 +751,9 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs) if (irq >= s->num_irq) { goto bad_reg; } - if (irq >= 29 && irq <= 31) { + if (irq < 29 && s->revision == REV_11MPCORE) { + res = 0; + } else if (irq < GIC_INTERNAL) { res = cm; } else { res = GIC_TARGET(irq); @@ -1014,7 +1016,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset, if (irq >= s->num_irq) { goto bad_reg; } - if (irq < 29) { + if (irq < 29 && s->revision == REV_11MPCORE) { value = 0; } else if (irq < GIC_INTERNAL) { value = ALL_CPU_MASK;
The GICD_ITARGETSR implementation still has some 11MPCore behaviour that we were incorrectly using in our GICv1 and GICv2 implementations for the case where the interrupt number is less than GIC_INTERNAL. The desired behaviour here is: * for 11MPCore: RAZ/WI for irqs 0..28; read a number matching the CPU doing the read for irqs 29..31 * for GICv1 and v2: RAZ/WI if uniprocessor; otherwise read a number matching the CPU doing the read for all irqs < 32 Stop squashing GICD_ITARGETSR to 0 for IRQs 0..28 unless this is an 11MPCore GIC. Reported-by: Jan Kiszka <jan.kiszka@web.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/intc/arm_gic.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)