| Message ID | 1529915453-4633-5-git-send-email-adouglas@cadence.com |
|---|---|
| State | Accepted |
| Delegated to: | Lorenzo Pieralisi |
| Headers | show |
| Series | PCI: cadence: Host and EP driver updates for PHY and power management | expand |
On Mon, Jun 25, 2018 at 09:30:52AM +0100, Alan Douglas wrote: > These PM ops will enable/disable the optional PHYs if present. The > AXI link-down register in the host driver is now cleared in > cdns_pci_map_bus since the link-down bit will be set if the PHY has > been disabled. It is not cleared when enabling the PHY, since the > link will not yet be up. It is not entirely clear what you mean here, can you elaborate please ? Thank you, Lorenzo > Signed-off-by: Alan Douglas <adouglas@cadence.com> > --- > drivers/pci/controller/pcie-cadence-ep.c | 1 + > drivers/pci/controller/pcie-cadence-host.c | 3 ++ > drivers/pci/controller/pcie-cadence.c | 30 ++++++++++++++++++++++++++++ > drivers/pci/controller/pcie-cadence.h | 4 +++ > 4 files changed, 38 insertions(+), 0 deletions(-) > > diff --git a/drivers/pci/controller/pcie-cadence-ep.c b/drivers/pci/controller/pcie-cadence-ep.c > index c02f33d..3eabd99 100644 > --- a/drivers/pci/controller/pcie-cadence-ep.c > +++ b/drivers/pci/controller/pcie-cadence-ep.c > @@ -555,6 +555,7 @@ static void cdns_pcie_ep_shutdown(struct platform_device *pdev) > .driver = { > .name = "cdns-pcie-ep", > .of_match_table = cdns_pcie_ep_of_match, > + .pm = &cdns_pcie_pm_ops, > }, > .probe = cdns_pcie_ep_probe, > .shutdown = cdns_pcie_ep_shutdown, > diff --git a/drivers/pci/controller/pcie-cadence-host.c b/drivers/pci/controller/pcie-cadence-host.c > index 36f3109..e3e9b7d 100644 > --- a/drivers/pci/controller/pcie-cadence-host.c > +++ b/drivers/pci/controller/pcie-cadence-host.c > @@ -61,6 +61,8 @@ struct cdns_pcie_rc { > /* Check that the link is up */ > if (!(cdns_pcie_readl(pcie, CDNS_PCIE_LM_BASE) & 0x1)) > return NULL; > + /* Clear AXI link-down status */ > + cdns_pcie_writel(pcie, CDNS_PCIE_AT_LINKDOWN, 0x0); > > /* Update Output registers for AXI region 0. */ > addr0 = CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(12) | > @@ -345,6 +347,7 @@ static int cdns_pcie_host_probe(struct platform_device *pdev) > .driver = { > .name = "cdns-pcie-host", > .of_match_table = cdns_pcie_host_of_match, > + .pm = &cdns_pcie_pm_ops, > }, > .probe = cdns_pcie_host_probe, > }; > diff --git a/drivers/pci/controller/pcie-cadence.c b/drivers/pci/controller/pcie-cadence.c > index 2edc126..86f1b00 100644 > --- a/drivers/pci/controller/pcie-cadence.c > +++ b/drivers/pci/controller/pcie-cadence.c > @@ -217,3 +217,33 @@ int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie) > > return ret; > } > + > +#ifdef CONFIG_PM_SLEEP > +static int cdns_pcie_suspend_noirq(struct device *dev) > +{ > + struct cdns_pcie *pcie = dev_get_drvdata(dev); > + > + cdns_pcie_disable_phy(pcie); > + > + return 0; > +} > + > +static int cdns_pcie_resume_noirq(struct device *dev) > +{ > + struct cdns_pcie *pcie = dev_get_drvdata(dev); > + int ret; > + > + ret = cdns_pcie_enable_phy(pcie); > + if (ret) { > + dev_err(dev, "failed to enable phy\n"); > + return ret; > + } > + > + return 0; > +} > +#endif > + > +const struct dev_pm_ops cdns_pcie_pm_ops = { > + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(cdns_pcie_suspend_noirq, > + cdns_pcie_resume_noirq) > +}; > diff --git a/drivers/pci/controller/pcie-cadence.h b/drivers/pci/controller/pcie-cadence.h > index b342c80..ae6bf2a 100644 > --- a/drivers/pci/controller/pcie-cadence.h > +++ b/drivers/pci/controller/pcie-cadence.h > @@ -166,6 +166,9 @@ > #define CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar) \ > (CDNS_PCIE_AT_BASE + 0x0804 + (bar) * 0x0008) > > +/* AXI link down register */ > +#define CDNS_PCIE_AT_LINKDOWN (CDNS_PCIE_AT_BASE + 0x0824) > + > enum cdns_pcie_rp_bar { > RP_BAR0, > RP_BAR1, > @@ -314,5 +317,6 @@ void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie, u8 fn, > void cdns_pcie_disable_phy(struct cdns_pcie *pcie); > int cdns_pcie_enable_phy(struct cdns_pcie *pcie); > int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie); > +extern const struct dev_pm_ops cdns_pcie_pm_ops; > > #endif /* _PCIE_CADENCE_H */ > -- > 1.7.1 >
On 09 July 2018 16:34, Lorenzo Pieralisi wrote: > On Mon, Jun 25, 2018 at 09:30:52AM +0100, Alan Douglas wrote: > > These PM ops will enable/disable the optional PHYs if present. The > > AXI link-down register in the host driver is now cleared in > > cdns_pci_map_bus since the link-down bit will be set if the PHY has > > been disabled. It is not cleared when enabling the PHY, since the > > link will not yet be up. > > It is not entirely clear what you mean here, can you elaborate please ? Thanks for taking a look at this. There is a "Link down indication bit" register in the cadence PCIe IP AXI Configuration Registers, which will be set by the PCIe IP after each link- down occurrence. This bit must be cleared before continuing, or accesses will hang. When the PHY is disabled, the link will go down and this bit will be set by HW. It will also be set after a secondary bus reset. We cannot simply clear this bit when enabling the PHY, since at this stage the link may not come up (e.g. because the EP PHY is disabled), and so we need to clear it on the first access after link-up. In order to ensure this, I simply clear it on every config access, in cdns_pci_map_bus, I couldn't think of a good way to just do it once. Regards, Alan > Thank you, > Lorenzo > > > Signed-off-by: Alan Douglas <adouglas@cadence.com> > > --- > > drivers/pci/controller/pcie-cadence-ep.c | 1 + > > drivers/pci/controller/pcie-cadence-host.c | 3 ++ > > drivers/pci/controller/pcie-cadence.c | 30 ++++++++++++++++++++++++++++ > > drivers/pci/controller/pcie-cadence.h | 4 +++ > > 4 files changed, 38 insertions(+), 0 deletions(-) > > > > diff --git a/drivers/pci/controller/pcie-cadence-ep.c b/drivers/pci/controller/pcie-cadence-ep.c > > index c02f33d..3eabd99 100644 > > --- a/drivers/pci/controller/pcie-cadence-ep.c > > +++ b/drivers/pci/controller/pcie-cadence-ep.c > > @@ -555,6 +555,7 @@ static void cdns_pcie_ep_shutdown(struct platform_device *pdev) > > .driver = { > > .name = "cdns-pcie-ep", > > .of_match_table = cdns_pcie_ep_of_match, > > + .pm = &cdns_pcie_pm_ops, > > }, > > .probe = cdns_pcie_ep_probe, > > .shutdown = cdns_pcie_ep_shutdown, > > diff --git a/drivers/pci/controller/pcie-cadence-host.c b/drivers/pci/controller/pcie-cadence-host.c > > index 36f3109..e3e9b7d 100644 > > --- a/drivers/pci/controller/pcie-cadence-host.c > > +++ b/drivers/pci/controller/pcie-cadence-host.c > > @@ -61,6 +61,8 @@ struct cdns_pcie_rc { > > /* Check that the link is up */ > > if (!(cdns_pcie_readl(pcie, CDNS_PCIE_LM_BASE) & 0x1)) > > return NULL; > > + /* Clear AXI link-down status */ > > + cdns_pcie_writel(pcie, CDNS_PCIE_AT_LINKDOWN, 0x0); > > > > /* Update Output registers for AXI region 0. */ > > addr0 = CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(12) | > > @@ -345,6 +347,7 @@ static int cdns_pcie_host_probe(struct platform_device *pdev) > > .driver = { > > .name = "cdns-pcie-host", > > .of_match_table = cdns_pcie_host_of_match, > > + .pm = &cdns_pcie_pm_ops, > > }, > > .probe = cdns_pcie_host_probe, > > }; > > diff --git a/drivers/pci/controller/pcie-cadence.c b/drivers/pci/controller/pcie-cadence.c > > index 2edc126..86f1b00 100644 > > --- a/drivers/pci/controller/pcie-cadence.c > > +++ b/drivers/pci/controller/pcie-cadence.c > > @@ -217,3 +217,33 @@ int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie) > > > > return ret; > > } > > + > > +#ifdef CONFIG_PM_SLEEP > > +static int cdns_pcie_suspend_noirq(struct device *dev) > > +{ > > + struct cdns_pcie *pcie = dev_get_drvdata(dev); > > + > > + cdns_pcie_disable_phy(pcie); > > + > > + return 0; > > +} > > + > > +static int cdns_pcie_resume_noirq(struct device *dev) > > +{ > > + struct cdns_pcie *pcie = dev_get_drvdata(dev); > > + int ret; > > + > > + ret = cdns_pcie_enable_phy(pcie); > > + if (ret) { > > + dev_err(dev, "failed to enable phy\n"); > > + return ret; > > + } > > + > > + return 0; > > +} > > +#endif > > + > > +const struct dev_pm_ops cdns_pcie_pm_ops = { > > + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(cdns_pcie_suspend_noirq, > > + cdns_pcie_resume_noirq) > > +}; > > diff --git a/drivers/pci/controller/pcie-cadence.h b/drivers/pci/controller/pcie-cadence.h > > index b342c80..ae6bf2a 100644 > > --- a/drivers/pci/controller/pcie-cadence.h > > +++ b/drivers/pci/controller/pcie-cadence.h > > @@ -166,6 +166,9 @@ > > #define CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar) \ > > (CDNS_PCIE_AT_BASE + 0x0804 + (bar) * 0x0008) > > > > +/* AXI link down register */ > > +#define CDNS_PCIE_AT_LINKDOWN (CDNS_PCIE_AT_BASE + 0x0824) > > + > > enum cdns_pcie_rp_bar { > > RP_BAR0, > > RP_BAR1, > > @@ -314,5 +317,6 @@ void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie, u8 fn, > > void cdns_pcie_disable_phy(struct cdns_pcie *pcie); > > int cdns_pcie_enable_phy(struct cdns_pcie *pcie); > > int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie); > > +extern const struct dev_pm_ops cdns_pcie_pm_ops; > > > > #endif /* _PCIE_CADENCE_H */ > > -- > > 1.7.1 > >
On Mon, Jul 09, 2018 at 03:56:11PM +0000, Alan Douglas wrote: > On 09 July 2018 16:34, Lorenzo Pieralisi wrote: > > On Mon, Jun 25, 2018 at 09:30:52AM +0100, Alan Douglas wrote: > > > These PM ops will enable/disable the optional PHYs if present. The > > > AXI link-down register in the host driver is now cleared in > > > cdns_pci_map_bus since the link-down bit will be set if the PHY has > > > been disabled. It is not cleared when enabling the PHY, since the > > > link will not yet be up. > > > > It is not entirely clear what you mean here, can you elaborate please ? > Thanks for taking a look at this. > There is a "Link down indication bit" register in the cadence PCIe IP > AXI Configuration Registers, which will be set by the PCIe IP after > each link- down occurrence. This bit must be cleared before > continuing, or accesses will hang. When the PHY is disabled, the link > will go down and this bit will be set by HW. It will also be set > after a secondary bus reset. > > We cannot simply clear this bit when enabling the PHY, since at this > stage the link may not come up (e.g. because the EP PHY is disabled), I understand the approach and the reasoning, I still would like to understand the use case that explains "because the EP PHY is disabled" above and, related to the same question, why isn't this needed in current driver version given that the host controller is probed out of reset, I will apply the series then and update the commit log. Lorenzo > and so we need to clear it on the first access after link-up. In order > to ensure this, I simply clear it on every config access, in > cdns_pci_map_bus, I couldn't think of a good way to just do it once. > > Regards, > Alan > > Thank you, > > Lorenzo > > > > > Signed-off-by: Alan Douglas <adouglas@cadence.com> > > > --- > > > drivers/pci/controller/pcie-cadence-ep.c | 1 + > > > drivers/pci/controller/pcie-cadence-host.c | 3 ++ > > > drivers/pci/controller/pcie-cadence.c | 30 ++++++++++++++++++++++++++++ > > > drivers/pci/controller/pcie-cadence.h | 4 +++ > > > 4 files changed, 38 insertions(+), 0 deletions(-) > > > > > > diff --git a/drivers/pci/controller/pcie-cadence-ep.c b/drivers/pci/controller/pcie-cadence-ep.c > > > index c02f33d..3eabd99 100644 > > > --- a/drivers/pci/controller/pcie-cadence-ep.c > > > +++ b/drivers/pci/controller/pcie-cadence-ep.c > > > @@ -555,6 +555,7 @@ static void cdns_pcie_ep_shutdown(struct platform_device *pdev) > > > .driver = { > > > .name = "cdns-pcie-ep", > > > .of_match_table = cdns_pcie_ep_of_match, > > > + .pm = &cdns_pcie_pm_ops, > > > }, > > > .probe = cdns_pcie_ep_probe, > > > .shutdown = cdns_pcie_ep_shutdown, > > > diff --git a/drivers/pci/controller/pcie-cadence-host.c b/drivers/pci/controller/pcie-cadence-host.c > > > index 36f3109..e3e9b7d 100644 > > > --- a/drivers/pci/controller/pcie-cadence-host.c > > > +++ b/drivers/pci/controller/pcie-cadence-host.c > > > @@ -61,6 +61,8 @@ struct cdns_pcie_rc { > > > /* Check that the link is up */ > > > if (!(cdns_pcie_readl(pcie, CDNS_PCIE_LM_BASE) & 0x1)) > > > return NULL; > > > + /* Clear AXI link-down status */ > > > + cdns_pcie_writel(pcie, CDNS_PCIE_AT_LINKDOWN, 0x0); > > > > > > /* Update Output registers for AXI region 0. */ > > > addr0 = CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(12) | > > > @@ -345,6 +347,7 @@ static int cdns_pcie_host_probe(struct platform_device *pdev) > > > .driver = { > > > .name = "cdns-pcie-host", > > > .of_match_table = cdns_pcie_host_of_match, > > > + .pm = &cdns_pcie_pm_ops, > > > }, > > > .probe = cdns_pcie_host_probe, > > > }; > > > diff --git a/drivers/pci/controller/pcie-cadence.c b/drivers/pci/controller/pcie-cadence.c > > > index 2edc126..86f1b00 100644 > > > --- a/drivers/pci/controller/pcie-cadence.c > > > +++ b/drivers/pci/controller/pcie-cadence.c > > > @@ -217,3 +217,33 @@ int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie) > > > > > > return ret; > > > } > > > + > > > +#ifdef CONFIG_PM_SLEEP > > > +static int cdns_pcie_suspend_noirq(struct device *dev) > > > +{ > > > + struct cdns_pcie *pcie = dev_get_drvdata(dev); > > > + > > > + cdns_pcie_disable_phy(pcie); > > > + > > > + return 0; > > > +} > > > + > > > +static int cdns_pcie_resume_noirq(struct device *dev) > > > +{ > > > + struct cdns_pcie *pcie = dev_get_drvdata(dev); > > > + int ret; > > > + > > > + ret = cdns_pcie_enable_phy(pcie); > > > + if (ret) { > > > + dev_err(dev, "failed to enable phy\n"); > > > + return ret; > > > + } > > > + > > > + return 0; > > > +} > > > +#endif > > > + > > > +const struct dev_pm_ops cdns_pcie_pm_ops = { > > > + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(cdns_pcie_suspend_noirq, > > > + cdns_pcie_resume_noirq) > > > +}; > > > diff --git a/drivers/pci/controller/pcie-cadence.h b/drivers/pci/controller/pcie-cadence.h > > > index b342c80..ae6bf2a 100644 > > > --- a/drivers/pci/controller/pcie-cadence.h > > > +++ b/drivers/pci/controller/pcie-cadence.h > > > @@ -166,6 +166,9 @@ > > > #define CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar) \ > > > (CDNS_PCIE_AT_BASE + 0x0804 + (bar) * 0x0008) > > > > > > +/* AXI link down register */ > > > +#define CDNS_PCIE_AT_LINKDOWN (CDNS_PCIE_AT_BASE + 0x0824) > > > + > > > enum cdns_pcie_rp_bar { > > > RP_BAR0, > > > RP_BAR1, > > > @@ -314,5 +317,6 @@ void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie, u8 fn, > > > void cdns_pcie_disable_phy(struct cdns_pcie *pcie); > > > int cdns_pcie_enable_phy(struct cdns_pcie *pcie); > > > int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie); > > > +extern const struct dev_pm_ops cdns_pcie_pm_ops; > > > > > > #endif /* _PCIE_CADENCE_H */ > > > -- > > > 1.7.1 > > >
On 11 July 2018 11:58, Lorenzo Pieralisi wrote: > On Mon, Jul 09, 2018 at 03:56:11PM +0000, Alan Douglas wrote: > > On 09 July 2018 16:34, Lorenzo Pieralisi wrote: > > > On Mon, Jun 25, 2018 at 09:30:52AM +0100, Alan Douglas wrote: > > > > These PM ops will enable/disable the optional PHYs if present. The > > > > AXI link-down register in the host driver is now cleared in > > > > cdns_pci_map_bus since the link-down bit will be set if the PHY has > > > > been disabled. It is not cleared when enabling the PHY, since the > > > > link will not yet be up. > > > > > > It is not entirely clear what you mean here, can you elaborate please ? > > Thanks for taking a look at this. > > There is a "Link down indication bit" register in the cadence PCIe IP > > AXI Configuration Registers, which will be set by the PCIe IP after > > each link- down occurrence. This bit must be cleared before > > continuing, or accesses will hang. When the PHY is disabled, the link > > will go down and this bit will be set by HW. It will also be set > > after a secondary bus reset. > > > > We cannot simply clear this bit when enabling the PHY, since at this > > stage the link may not come up (e.g. because the EP PHY is disabled), > > I understand the approach and the reasoning, I still would like to > understand the use case that explains "because the EP PHY is disabled" > above and, related to the same question, why isn't this needed in > current driver version given that the host controller is probed out > of reset, I will apply the series then and update the commit log. > > Lorenzo > Why isn't it needed with current? The current driver version can only be used where there is no Linux PHY required (e.g. in simulation or if the PHY was controlled in hardware or firmware.) Right now, I'm only aware of this driver being used in simulation and the only use-case that will lead to link-down is a secondary bus reset. In this case, there is a recovery time, and the PCIe HW can be configured to clear the link-down indication bit during that time using a hardware timer. If there is an implementation with the PHY controlled by hardware or firmware, the link-down indication bit should also be cleared external to the Linux driver. Use-case? The addition of PHY & PM ops to the driver allows it to be used for hw where the PHY is not being managed externally. There is a possible use case where two cadence RP & EP are running in a back-to-back configuration, and the link will not be established until both PHY have been enabled. At first power-up this is fine, because the link will not have gone down, and the link-down bit will not be set. During suspend/resume, the RP and EP will both power-down/up their respective PHYs, and so the link-down bit will be set. However, the EP will not power up its PHY until its resume is called, and this may be after the RP. This is what I mean by: "e.g. because the EP PHY is disabled", i.e. it's still disabled while resuming the RP. Thanks for asking about this, hope the explanation makes sense. One thing that I am now wondering about is the validity of powering down/up the EP PHY when handling suspend/resume. > > and so we need to clear it on the first access after link-up. In order > > to ensure this, I simply clear it on every config access, in > > cdns_pci_map_bus, I couldn't think of a good way to just do it once. > > > > Regards, > > Alan > > > Thank you, > > > Lorenzo > > > > > > > Signed-off-by: Alan Douglas <adouglas@cadence.com> > > > > --- > > > > drivers/pci/controller/pcie-cadence-ep.c | 1 + > > > > drivers/pci/controller/pcie-cadence-host.c | 3 ++ > > > > drivers/pci/controller/pcie-cadence.c | 30 ++++++++++++++++++++++++++++ > > > > drivers/pci/controller/pcie-cadence.h | 4 +++ > > > > 4 files changed, 38 insertions(+), 0 deletions(-) > > > > > > > > diff --git a/drivers/pci/controller/pcie-cadence-ep.c b/drivers/pci/controller/pcie-cadence-ep.c > > > > index c02f33d..3eabd99 100644 > > > > --- a/drivers/pci/controller/pcie-cadence-ep.c > > > > +++ b/drivers/pci/controller/pcie-cadence-ep.c > > > > @@ -555,6 +555,7 @@ static void cdns_pcie_ep_shutdown(struct platform_device *pdev) > > > > .driver = { > > > > .name = "cdns-pcie-ep", > > > > .of_match_table = cdns_pcie_ep_of_match, > > > > + .pm = &cdns_pcie_pm_ops, > > > > }, > > > > .probe = cdns_pcie_ep_probe, > > > > .shutdown = cdns_pcie_ep_shutdown, > > > > diff --git a/drivers/pci/controller/pcie-cadence-host.c b/drivers/pci/controller/pcie-cadence-host.c > > > > index 36f3109..e3e9b7d 100644 > > > > --- a/drivers/pci/controller/pcie-cadence-host.c > > > > +++ b/drivers/pci/controller/pcie-cadence-host.c > > > > @@ -61,6 +61,8 @@ struct cdns_pcie_rc { > > > > /* Check that the link is up */ > > > > if (!(cdns_pcie_readl(pcie, CDNS_PCIE_LM_BASE) & 0x1)) > > > > return NULL; > > > > + /* Clear AXI link-down status */ > > > > + cdns_pcie_writel(pcie, CDNS_PCIE_AT_LINKDOWN, 0x0); > > > > > > > > /* Update Output registers for AXI region 0. */ > > > > addr0 = CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(12) | > > > > @@ -345,6 +347,7 @@ static int cdns_pcie_host_probe(struct platform_device *pdev) > > > > .driver = { > > > > .name = "cdns-pcie-host", > > > > .of_match_table = cdns_pcie_host_of_match, > > > > + .pm = &cdns_pcie_pm_ops, > > > > }, > > > > .probe = cdns_pcie_host_probe, > > > > }; > > > > diff --git a/drivers/pci/controller/pcie-cadence.c b/drivers/pci/controller/pcie-cadence.c > > > > index 2edc126..86f1b00 100644 > > > > --- a/drivers/pci/controller/pcie-cadence.c > > > > +++ b/drivers/pci/controller/pcie-cadence.c > > > > @@ -217,3 +217,33 @@ int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie) > > > > > > > > return ret; > > > > } > > > > + > > > > +#ifdef CONFIG_PM_SLEEP > > > > +static int cdns_pcie_suspend_noirq(struct device *dev) > > > > +{ > > > > + struct cdns_pcie *pcie = dev_get_drvdata(dev); > > > > + > > > > + cdns_pcie_disable_phy(pcie); > > > > + > > > > + return 0; > > > > +} > > > > + > > > > +static int cdns_pcie_resume_noirq(struct device *dev) > > > > +{ > > > > + struct cdns_pcie *pcie = dev_get_drvdata(dev); > > > > + int ret; > > > > + > > > > + ret = cdns_pcie_enable_phy(pcie); > > > > + if (ret) { > > > > + dev_err(dev, "failed to enable phy\n"); > > > > + return ret; > > > > + } > > > > + > > > > + return 0; > > > > +} > > > > +#endif > > > > + > > > > +const struct dev_pm_ops cdns_pcie_pm_ops = { > > > > + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(cdns_pcie_suspend_noirq, > > > > + cdns_pcie_resume_noirq) > > > > +}; > > > > diff --git a/drivers/pci/controller/pcie-cadence.h b/drivers/pci/controller/pcie-cadence.h > > > > index b342c80..ae6bf2a 100644 > > > > --- a/drivers/pci/controller/pcie-cadence.h > > > > +++ b/drivers/pci/controller/pcie-cadence.h > > > > @@ -166,6 +166,9 @@ > > > > #define CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar) \ > > > > (CDNS_PCIE_AT_BASE + 0x0804 + (bar) * 0x0008) > > > > > > > > +/* AXI link down register */ > > > > +#define CDNS_PCIE_AT_LINKDOWN (CDNS_PCIE_AT_BASE + 0x0824) > > > > + > > > > enum cdns_pcie_rp_bar { > > > > RP_BAR0, > > > > RP_BAR1, > > > > @@ -314,5 +317,6 @@ void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie, u8 fn, > > > > void cdns_pcie_disable_phy(struct cdns_pcie *pcie); > > > > int cdns_pcie_enable_phy(struct cdns_pcie *pcie); > > > > int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie); > > > > +extern const struct dev_pm_ops cdns_pcie_pm_ops; > > > > > > > > #endif /* _PCIE_CADENCE_H */ > > > > -- > > > > 1.7.1 > > > >
diff --git a/drivers/pci/controller/pcie-cadence-ep.c b/drivers/pci/controller/pcie-cadence-ep.c index c02f33d..3eabd99 100644 --- a/drivers/pci/controller/pcie-cadence-ep.c +++ b/drivers/pci/controller/pcie-cadence-ep.c @@ -555,6 +555,7 @@ static void cdns_pcie_ep_shutdown(struct platform_device *pdev) .driver = { .name = "cdns-pcie-ep", .of_match_table = cdns_pcie_ep_of_match, + .pm = &cdns_pcie_pm_ops, }, .probe = cdns_pcie_ep_probe, .shutdown = cdns_pcie_ep_shutdown, diff --git a/drivers/pci/controller/pcie-cadence-host.c b/drivers/pci/controller/pcie-cadence-host.c index 36f3109..e3e9b7d 100644 --- a/drivers/pci/controller/pcie-cadence-host.c +++ b/drivers/pci/controller/pcie-cadence-host.c @@ -61,6 +61,8 @@ struct cdns_pcie_rc { /* Check that the link is up */ if (!(cdns_pcie_readl(pcie, CDNS_PCIE_LM_BASE) & 0x1)) return NULL; + /* Clear AXI link-down status */ + cdns_pcie_writel(pcie, CDNS_PCIE_AT_LINKDOWN, 0x0); /* Update Output registers for AXI region 0. */ addr0 = CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(12) | @@ -345,6 +347,7 @@ static int cdns_pcie_host_probe(struct platform_device *pdev) .driver = { .name = "cdns-pcie-host", .of_match_table = cdns_pcie_host_of_match, + .pm = &cdns_pcie_pm_ops, }, .probe = cdns_pcie_host_probe, }; diff --git a/drivers/pci/controller/pcie-cadence.c b/drivers/pci/controller/pcie-cadence.c index 2edc126..86f1b00 100644 --- a/drivers/pci/controller/pcie-cadence.c +++ b/drivers/pci/controller/pcie-cadence.c @@ -217,3 +217,33 @@ int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie) return ret; } + +#ifdef CONFIG_PM_SLEEP +static int cdns_pcie_suspend_noirq(struct device *dev) +{ + struct cdns_pcie *pcie = dev_get_drvdata(dev); + + cdns_pcie_disable_phy(pcie); + + return 0; +} + +static int cdns_pcie_resume_noirq(struct device *dev) +{ + struct cdns_pcie *pcie = dev_get_drvdata(dev); + int ret; + + ret = cdns_pcie_enable_phy(pcie); + if (ret) { + dev_err(dev, "failed to enable phy\n"); + return ret; + } + + return 0; +} +#endif + +const struct dev_pm_ops cdns_pcie_pm_ops = { + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(cdns_pcie_suspend_noirq, + cdns_pcie_resume_noirq) +}; diff --git a/drivers/pci/controller/pcie-cadence.h b/drivers/pci/controller/pcie-cadence.h index b342c80..ae6bf2a 100644 --- a/drivers/pci/controller/pcie-cadence.h +++ b/drivers/pci/controller/pcie-cadence.h @@ -166,6 +166,9 @@ #define CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar) \ (CDNS_PCIE_AT_BASE + 0x0804 + (bar) * 0x0008) +/* AXI link down register */ +#define CDNS_PCIE_AT_LINKDOWN (CDNS_PCIE_AT_BASE + 0x0824) + enum cdns_pcie_rp_bar { RP_BAR0, RP_BAR1, @@ -314,5 +317,6 @@ void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie, u8 fn, void cdns_pcie_disable_phy(struct cdns_pcie *pcie); int cdns_pcie_enable_phy(struct cdns_pcie *pcie); int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie); +extern const struct dev_pm_ops cdns_pcie_pm_ops; #endif /* _PCIE_CADENCE_H */
These PM ops will enable/disable the optional PHYs if present. The AXI link-down register in the host driver is now cleared in cdns_pci_map_bus since the link-down bit will be set if the PHY has been disabled. It is not cleared when enabling the PHY, since the link will not yet be up. Signed-off-by: Alan Douglas <adouglas@cadence.com> --- drivers/pci/controller/pcie-cadence-ep.c | 1 + drivers/pci/controller/pcie-cadence-host.c | 3 ++ drivers/pci/controller/pcie-cadence.c | 30 ++++++++++++++++++++++++++++ drivers/pci/controller/pcie-cadence.h | 4 +++ 4 files changed, 38 insertions(+), 0 deletions(-)