| Message ID | 1528801355-18719-2-git-send-email-tdas@codeaurora.org |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | cpufreq: qcom-fw: Add support for QCOM cpufreq FW driver | expand |
On 12/06/18 12:02, Taniya Das wrote: > Add QCOM cpufreq firmware device bindings for Qualcomm Technology Inc's > SoCs. This is required for managing the cpu frequency transitions which are > controlled by firmware. > > Signed-off-by: Taniya Das <tdas@codeaurora.org> > --- > .../bindings/cpufreq/cpufreq-qcom-fw.txt | 173 +++++++++++++++++++++ > 1 file changed, 173 insertions(+) > create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-fw.txt > > diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-fw.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-fw.txt > new file mode 100644 > index 0000000..e3087ec > --- /dev/null > +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-fw.txt > @@ -0,0 +1,173 @@ > +Qualcomm Technologies, Inc. CPUFREQ Bindings > + > +CPUFREQ FW is a hardware engine used by some Qualcomm Technologies, Inc. (QTI) > +SoCs to manage frequency in hardware. It is capable of controlling frequency > +for multiple clusters. > + You are bit inconsistent on the wordings. Some places you refer this as hardware engine. If so, please drop all references to firmware/FW. If it's firmware then update accordingly. > +Properties: > +- compatible > + Usage: required > + Value type: <string> > + Definition: must be "qcom,cpufreq-fw". > + > +* Property qcom,freq-domain > +Devices supporting freq-domain must set their "qcom,freq-domain" property with > +phandle to a freq_domain_table in their DT node. > + > +* Frequency Domain Table Node > + > +This describes the frequency domain belonging to a device. > +This node can have following properties: > + > +- reg > + Usage: required > + Value type: <prop-encoded-array> > + Definition: Addresses and sizes for the memory of the perf > + , lut and enable bases. > + perf - indicates the base address for the desired > + performance state to be set. > + lut - indicates the look up table base address for the > + cpufreq driver to read frequencies. > + enable - indicates the enable register for firmware. You still didn't answer my earlier question. OS might touch one or 2 registers in lots of IP blocks. I am not sure why those are any different from these. Are you trying to align with any other bindings or specification. Are you trying to make this binding generic here ? I understand if it was trying to generalize the firmware interface, but you also state it's a hardware engine. So I fail to see the need for such specificity here. Why not define the whole IP block and the driver knows where to access these specific ones as they are specific to this hardware block. In that way if you decide to add more data, it's extensible easily without the need for patching DT. Eg. Suppose you need some information on power curve for EAS energy model, I really hate to update DT for that or even do a mix with DT just because f/w is no longer modifiable.
Hello Sudeep, Thanks for review comments. On 6/13/2018 4:56 PM, Sudeep Holla wrote: > > > On 12/06/18 12:02, Taniya Das wrote: >> Add QCOM cpufreq firmware device bindings for Qualcomm Technology Inc's >> SoCs. This is required for managing the cpu frequency transitions which are >> controlled by firmware. >> >> Signed-off-by: Taniya Das <tdas@codeaurora.org> >> --- >> .../bindings/cpufreq/cpufreq-qcom-fw.txt | 173 +++++++++++++++++++++ >> 1 file changed, 173 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-fw.txt >> >> diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-fw.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-fw.txt >> new file mode 100644 >> index 0000000..e3087ec >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-fw.txt >> @@ -0,0 +1,173 @@ >> +Qualcomm Technologies, Inc. CPUFREQ Bindings >> + >> +CPUFREQ FW is a hardware engine used by some Qualcomm Technologies, Inc. (QTI) >> +SoCs to manage frequency in hardware. It is capable of controlling frequency >> +for multiple clusters. >> + > > You are bit inconsistent on the wordings. Some places you refer this as > hardware engine. If so, please drop all references to firmware/FW. If > it's firmware then update accordingly. > It is a hardware engine which has a firmware to take care of the managing the frequency request from OS. That is reason to refer it as a firmware. >> +Properties: >> +- compatible >> + Usage: required >> + Value type: <string> >> + Definition: must be "qcom,cpufreq-fw". >> + >> +* Property qcom,freq-domain >> +Devices supporting freq-domain must set their "qcom,freq-domain" property with >> +phandle to a freq_domain_table in their DT node. >> + >> +* Frequency Domain Table Node >> + >> +This describes the frequency domain belonging to a device. >> +This node can have following properties: >> + >> +- reg >> + Usage: required >> + Value type: <prop-encoded-array> >> + Definition: Addresses and sizes for the memory of the perf >> + , lut and enable bases. >> + perf - indicates the base address for the desired >> + performance state to be set. >> + lut - indicates the look up table base address for the >> + cpufreq driver to read frequencies. >> + enable - indicates the enable register for firmware. > > > You still didn't answer my earlier question. > > OS might touch one or 2 registers in lots of IP blocks. I am not sure > why those are any different from these. Are you trying to align with any > other bindings or specification. Are you trying to make this binding > generic here ? I understand if it was trying to generalize the firmware > interface, but you also state it's a hardware engine. So I fail to see > the need for such specificity here. Why not define the whole IP block > and the driver knows where to access these specific ones as they are > specific to this hardware block. In that way if you decide to add more > data, it's extensible easily without the need for patching DT. > Sorry Sudeep I missed replying to your earlier query. The High level OS(HLOS) would require to access only these specific registers from this IP block and just mapping the whole block(huge region) is unnecessary from the OS point of View. As of now it is a generic binding for all using this IP block to manage frequency requests. The OS would only have to know the frequencies supported i.e to read the lookup table registers and put across the OS request using the performance state register. > Eg. Suppose you need some information on power curve for EAS energy > model, I really hate to update DT for that or even do a mix with DT just > because f/w is no longer modifiable. > For now we are safe.
On 13/06/18 19:13, Taniya Das wrote: > Hello Sudeep, > > Thanks for review comments. > > On 6/13/2018 4:56 PM, Sudeep Holla wrote: >> >> [...] >> You are bit inconsistent on the wordings. Some places you refer this as >> hardware engine. If so, please drop all references to firmware/FW. If >> it's firmware then update accordingly. >> > > It is a hardware engine which has a firmware to take care of the > managing the frequency request from OS. That is reason to refer it as a > firmware. > Yes I did guess that initially, but I failed to understand when different bindings were posted to deal with devfreq and cpufreq with the same firmware. Ideally if it's the firmware you are talking to, place all these under /firmware node and align all those with single binding. Is there anything else that this firmware deals with ? If so all those need to be put in one place. >>> +Properties: >>> +- compatible >>> + Usage: required >>> + Value type: <string> >>> + Definition: must be "qcom,cpufreq-fw". >>> + >>> +* Property qcom,freq-domain >>> +Devices supporting freq-domain must set their "qcom,freq-domain" >>> property with >>> +phandle to a freq_domain_table in their DT node. >>> + >>> +* Frequency Domain Table Node >>> + >>> +This describes the frequency domain belonging to a device. >>> +This node can have following properties: >>> + >>> +- reg >>> + Usage: required >>> + Value type: <prop-encoded-array> >>> + Definition: Addresses and sizes for the memory of the perf >>> + , lut and enable bases. >>> + perf - indicates the base address for the desired >>> + performance state to be set. >>> + lut - indicates the look up table base address for the >>> + cpufreq driver to read frequencies. >>> + enable - indicates the enable register for firmware. >> >> >> You still didn't answer my earlier question. >> >> OS might touch one or 2 registers in lots of IP blocks. I am not sure >> why those are any different from these. Are you trying to align with any >> other bindings or specification. Are you trying to make this binding >> generic here ? I understand if it was trying to generalize the firmware >> interface, but you also state it's a hardware engine. So I fail to see >> the need for such specificity here. Why not define the whole IP block >> and the driver knows where to access these specific ones as they are >> specific to this hardware block. In that way if you decide to add more >> data, it's extensible easily without the need for patching DT. >> > > Sorry Sudeep I missed replying to your earlier query. > The High level OS(HLOS) would require to access only these specific > registers from this IP block and just mapping the whole block(huge > region) is unnecessary from the OS point of View. As of now it is a > generic binding for all using this IP block to manage frequency > requests. The OS would only have to know the frequencies supported i.e > to read the lookup table registers and put across the OS request using > the performance state register. > I am not sure if you need to defining bindings to save OSPM IO mapping. In-fact you may be adding more mapping unnecessarily. The mappings are page aligned and spiting the registers and mapping them individually may result in more mappings. I just need to know the rational for such specific choice of registers. I assume it's aligned to some other standard specifications like CPPC though not identical. >> Eg. Suppose you need some information on power curve for EAS energy >> model, I really hate to update DT for that or even do a mix with DT just >> because f/w is no longer modifiable. >> > > For now we are safe. > What do you mean by that ? It should be easily extensible is what I am trying to say. You can add more info and alter the information in the driver with compatibles if you keep the register info as minimum as possible. For now, you have enable, set and lut registers. What if you want to provide power numbers ?
Hello Sudeep, Thanks for your comments. On 6/14/2018 4:17 PM, Sudeep Holla wrote: > > > On 13/06/18 19:13, Taniya Das wrote: >> Hello Sudeep, >> >> Thanks for review comments. >> >> On 6/13/2018 4:56 PM, Sudeep Holla wrote: >>> >>> > > [...] > >>> You are bit inconsistent on the wordings. Some places you refer this as >>> hardware engine. If so, please drop all references to firmware/FW. If >>> it's firmware then update accordingly. >>> >> >> It is a hardware engine which has a firmware to take care of the >> managing the frequency request from OS. That is reason to refer it as a >> firmware. >> > > Yes I did guess that initially, but I failed to understand when > different bindings were posted to deal with devfreq and cpufreq with the > same firmware. Ideally if it's the firmware you are talking to, place > all these under /firmware node and align all those with single binding. > The OS is not aware of the firmware and OS only knows about the hardware engine and has to put forward it's request to the hardware engine using the "Perf" state register in both devfreq & cpufreq. So would it be still required to put under the /firmware node? > Is there anything else that this firmware deals with ? If so all those > need to be put in one place. > We deal only with the CPU frequency and L3 frequency(devfreq). >>>> +Properties: >>>> +- compatible >>>> + Usage: required >>>> + Value type: <string> >>>> + Definition: must be "qcom,cpufreq-fw". >>>> + >>>> +* Property qcom,freq-domain >>>> +Devices supporting freq-domain must set their "qcom,freq-domain" >>>> property with >>>> +phandle to a freq_domain_table in their DT node. >>>> + >>>> +* Frequency Domain Table Node >>>> + >>>> +This describes the frequency domain belonging to a device. >>>> +This node can have following properties: >>>> + >>>> +- reg >>>> + Usage: required >>>> + Value type: <prop-encoded-array> >>>> + Definition: Addresses and sizes for the memory of the perf >>>> + , lut and enable bases. >>>> + perf - indicates the base address for the desired >>>> + performance state to be set. >>>> + lut - indicates the look up table base address for the >>>> + cpufreq driver to read frequencies. >>>> + enable - indicates the enable register for firmware. >>> >>> >>> You still didn't answer my earlier question. >>> >>> OS might touch one or 2 registers in lots of IP blocks. I am not sure >>> why those are any different from these. Are you trying to align with any >>> other bindings or specification. Are you trying to make this binding >>> generic here ? I understand if it was trying to generalize the firmware >>> interface, but you also state it's a hardware engine. So I fail to see >>> the need for such specificity here. Why not define the whole IP block >>> and the driver knows where to access these specific ones as they are >>> specific to this hardware block. In that way if you decide to add more >>> data, it's extensible easily without the need for patching DT. >>> >> >> Sorry Sudeep I missed replying to your earlier query. >> The High level OS(HLOS) would require to access only these specific >> registers from this IP block and just mapping the whole block(huge >> region) is unnecessary from the OS point of View. As of now it is a >> generic binding for all using this IP block to manage frequency >> requests. The OS would only have to know the frequencies supported i.e >> to read the lookup table registers and put across the OS request using >> the performance state register. >> > > I am not sure if you need to defining bindings to save OSPM IO mapping. > In-fact you may be adding more mapping unnecessarily. The mappings are > page aligned and spiting the registers and mapping them individually may > result in more mappings. > > I just need to know the rational for such specific choice of registers. > I assume it's aligned to some other standard specifications like CPPC > though not identical. > I am not sure of the query but there is no other register that the OS is required to use other than the ones defined here. >>> Eg. Suppose you need some information on power curve for EAS energy >>> model, I really hate to update DT for that or even do a mix with DT just >>> because f/w is no longer modifiable. >>> >> >> For now we are safe. >> > > What do you mean by that ? I meant here was currently there is no such known case where the f/w is no longer modifiable and we need to extend device tree bindings. > It should be easily extensible is what I am > trying to say. You can add more info and alter the information in the > driver with compatibles if you keep the register info as minimum as > possible. For now, you have enable, set and lut registers. What if you > want to provide power numbers ? > Yes I do understand the intent of mapping the whole register space, but as per the HW specs these 3 registers would be the only ones required for now. I do not think this hardware engine has any information on the power numbers.
On Thu, Jun 14, 2018 at 9:24 PM, Taniya Das <tdas@codeaurora.org> wrote: >>> Sorry Sudeep I missed replying to your earlier query. >>> The High level OS(HLOS) would require to access only these specific >>> registers from this IP block and just mapping the whole block(huge >>> region) is unnecessary from the OS point of View. As of now it is a >>> generic binding for all using this IP block to manage frequency >>> requests. The OS would only have to know the frequencies supported i.e >>> to read the lookup table registers and put across the OS request using >>> the performance state register. >>> >> >> I am not sure if you need to defining bindings to save OSPM IO mapping. >> In-fact you may be adding more mapping unnecessarily. The mappings are >> page aligned and spiting the registers and mapping them individually may >> result in more mappings. >> >> I just need to know the rational for such specific choice of registers. >> I assume it's aligned to some other standard specifications like CPPC >> though not identical. >> > > I am not sure of the query but there is no other register that the OS is > required to use other than the ones defined here. > >>>> Eg. Suppose you need some information on power curve for EAS energy >>>> model, I really hate to update DT for that or even do a mix with DT just >>>> because f/w is no longer modifiable. >>>> >>> >>> For now we are safe. >>> >> >> What do you mean by that ? > > > I meant here was currently there is no such known case where the f/w is no > longer modifiable and we need to extend device tree bindings. > >> It should be easily extensible is what I am >> trying to say. You can add more info and alter the information in the >> driver with compatibles if you keep the register info as minimum as >> possible. For now, you have enable, set and lut registers. What if you >> want to provide power numbers ? >> > > Yes I do understand the intent of mapping the whole register space, but as > per the HW specs these 3 registers would be the only ones required for now. > I do not think this hardware engine has any information on the power > numbers. "For now" - I think this is exactly the point that Sudeep is trying to make. A future version of the HW engine, or more likely, a firmware revision, will make more functionality available. Say, this needs access to another register or two. This will require changing the DT bindings. Instead, if you map the entire address space, you can just add offsets to the new registers. So in this case, I think you should define the following addresses (size 0x1400) for the two frequency domains 0x17d43000, 0x1400 (power cluster) 0x17d45800, 0x1400 (perf cluster) And in the driver simply add offsets as follows: #define ENABLE_OFFSET 0x0 #define LUT_OFFSET 0x110 #define PERF_DESIRED_OFFSET 0x920 This will allow you add any new registers in the future w/o modifying the DT binding and reduce qcom_cpu_resources_init() to a handful of lines since you no longer need so many OF string matches, and devm_ioremap()s. Regards, Amit -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Tue, Jun 12, 2018 at 2:02 PM, Taniya Das <tdas@codeaurora.org> wrote: > Add QCOM cpufreq firmware device bindings for Qualcomm Technology Inc's > SoCs. This is required for managing the cpu frequency transitions which are > controlled by firmware. > > Signed-off-by: Taniya Das <tdas@codeaurora.org> > + qcom,cpufreq-fw { > + compatible = "qcom,cpufreq-fw"; > + > + #address-cells = <1>; > + #size-cells = <1>; > + > + freq_domain_table0 : freq_table0 { > + reg = <0x17d43920 0x4>, <0x17d43110 0x500>, > + <0x17d41000 0x4>; Changing the enable address to 0x17d43000 would make this a working example, I think. > + reg-names = "perf", "lut", "enable"; > + }; > + > + freq_domain_table1 : freq_table1 { > + reg = <0x17d46120 0x4>, <0x17d45910 0x500>, > + <0x17d45800 0x4> ; > + reg-names = "perf", "lut", "enable"; > + }; > + }; -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 14/06/18 19:24, Taniya Das wrote: > Hello Sudeep, > > Thanks for your comments. > > On 6/14/2018 4:17 PM, Sudeep Holla wrote: >> >> >> On 13/06/18 19:13, Taniya Das wrote: >>> Hello Sudeep, >>> >>> Thanks for review comments. >>> >>> On 6/13/2018 4:56 PM, Sudeep Holla wrote: >>>> >>>> >> >> [...] >> >>>> You are bit inconsistent on the wordings. Some places you refer this as >>>> hardware engine. If so, please drop all references to firmware/FW. If >>>> it's firmware then update accordingly. >>>> >>> >>> It is a hardware engine which has a firmware to take care of the >>> managing the frequency request from OS. That is reason to refer it as a >>> firmware. >>> >> >> Yes I did guess that initially, but I failed to understand when >> different bindings were posted to deal with devfreq and cpufreq with the >> same firmware. Ideally if it's the firmware you are talking to, place >> all these under /firmware node and align all those with single binding. >> > > The OS is not aware of the firmware and OS only knows about the hardware > engine and has to put forward it's request to the hardware engine using > the "Perf" state register in both devfreq & cpufreq. So would it be > still required to put under the /firmware node? > Ah ok, then remove any references to firmware other than stating its presence in the introduction. E.g. you have "Add cpufreq firmware device bindings ...". So this is definitely not firmware binding. You are just presenting the h/w as is and you need to deal with change of firmware in DT and OS agnostic way. >> Is there anything else that this firmware deals with ? If so all those >> need to be put in one place. >> > > We deal only with the CPU frequency and L3 frequency(devfreq). > OK >>>>> +Properties: >>>>> +- compatible >>>>> + Usage: required >>>>> + Value type: <string> >>>>> + Definition: must be "qcom,cpufreq-fw". >>>>> + >>>>> +* Property qcom,freq-domain >>>>> +Devices supporting freq-domain must set their "qcom,freq-domain" >>>>> property with >>>>> +phandle to a freq_domain_table in their DT node. >>>>> + >>>>> +* Frequency Domain Table Node >>>>> + >>>>> +This describes the frequency domain belonging to a device. >>>>> +This node can have following properties: >>>>> + >>>>> +- reg >>>>> + Usage: required >>>>> + Value type: <prop-encoded-array> >>>>> + Definition: Addresses and sizes for the memory of the perf >>>>> + , lut and enable bases. >>>>> + perf - indicates the base address for the desired >>>>> + performance state to be set. >>>>> + lut - indicates the look up table base address for the >>>>> + cpufreq driver to read frequencies. >>>>> + enable - indicates the enable register for firmware. >>>> >>>> >>>> You still didn't answer my earlier question. >>>> >>>> OS might touch one or 2 registers in lots of IP blocks. I am not sure >>>> why those are any different from these. Are you trying to align with >>>> any >>>> other bindings or specification. Are you trying to make this binding >>>> generic here ? I understand if it was trying to generalize the firmware >>>> interface, but you also state it's a hardware engine. So I fail to see >>>> the need for such specificity here. Why not define the whole IP block >>>> and the driver knows where to access these specific ones as they are >>>> specific to this hardware block. In that way if you decide to add more >>>> data, it's extensible easily without the need for patching DT. >>>> >>> >>> Sorry Sudeep I missed replying to your earlier query. >>> The High level OS(HLOS) would require to access only these specific >>> registers from this IP block and just mapping the whole block(huge >>> region) is unnecessary from the OS point of View. As of now it is a >>> generic binding for all using this IP block to manage frequency >>> requests. The OS would only have to know the frequencies supported i.e >>> to read the lookup table registers and put across the OS request using >>> the performance state register. >>> >> >> I am not sure if you need to defining bindings to save OSPM IO mapping. >> In-fact you may be adding more mapping unnecessarily. The mappings are >> page aligned and spiting the registers and mapping them individually may >> result in more mappings. >> >> I just need to know the rational for such specific choice of registers. >> I assume it's aligned to some other standard specifications like CPPC >> though not identical. >> > > I am not sure of the query but there is no other register that the OS is > required to use other than the ones defined here. > The point is ever IP on the SoC may have 100s to 1000s of registers that may or may not be used by OS. That's about to the OS to decide and you just need to provide the hardware view to anyone using the device tree. It *should not* _just_ represent what you think OS(Linux in particular) "for now" >>>> Eg. Suppose you need some information on power curve for EAS energy >>>> model, I really hate to update DT for that or even do a mix with DT >>>> just >>>> because f/w is no longer modifiable. >>>> >>> >>> For now we are safe. >>> >> >> What do you mean by that ? > > I meant here was currently there is no such known case where the f/w is > no longer modifiable and we need to extend device tree bindings. > >> It should be easily extensible is what I am >> trying to say. You can add more info and alter the information in the >> driver with compatibles if you keep the register info as minimum as >> possible. For now, you have enable, set and lut registers. What if you >> want to provide power numbers ? >> > > Yes I do understand the intent of mapping the whole register space, but > as per the HW specs these 3 registers would be the only ones required > for now. I do not think this hardware engine has any information on the > power numbers. > That's fine. So on this platform DT, will you list only the registers touched by the OS for all the IP ? I am sure that will not be the case.
On 15/06/18 12:59, Amit Kucheria wrote: > On Thu, Jun 14, 2018 at 9:24 PM, Taniya Das <tdas@codeaurora.org> wrote: > [...] >> >> Yes I do understand the intent of mapping the whole register space, but as >> per the HW specs these 3 registers would be the only ones required for now. >> I do not think this hardware engine has any information on the power >> numbers. > > "For now" - I think this is exactly the point that Sudeep is trying to make. > > A future version of the HW engine, or more likely, a firmware > revision, will make more functionality available. Say, this needs > access to another register or two. This will require changing the DT > bindings. Instead, if you map the entire address space, you can just > add offsets to the new registers. > > So in this case, I think you should define the following addresses > (size 0x1400) for the two frequency domains > > 0x17d43000, 0x1400 (power cluster) > 0x17d45800, 0x1400 (perf cluster) > > And in the driver simply add offsets as follows: > > #define ENABLE_OFFSET 0x0 > #define LUT_OFFSET 0x110 > #define PERF_DESIRED_OFFSET 0x920 > > This will allow you add any new registers in the future w/o modifying > the DT binding and reduce qcom_cpu_resources_init() to a handful of > lines since you no longer need so many OF string matches, and > devm_ioremap()s. > Thanks Amit for such nice and detailed explanation. I was lazy to write in such details, but was hoping Taniya to understand the point. Anyways thanks again for doing this.
On 6/15/2018 6:53 PM, Sudeep Holla wrote: > > > On 14/06/18 19:24, Taniya Das wrote: >> Hello Sudeep, >> >> Thanks for your comments. >> >> On 6/14/2018 4:17 PM, Sudeep Holla wrote: >>> >>> >>> On 13/06/18 19:13, Taniya Das wrote: >>>> Hello Sudeep, >>>> >>>> Thanks for review comments. >>>> >>>> On 6/13/2018 4:56 PM, Sudeep Holla wrote: >>>>> >>>>> >>> >>> [...] >>> >>>>> You are bit inconsistent on the wordings. Some places you refer this as >>>>> hardware engine. If so, please drop all references to firmware/FW. If >>>>> it's firmware then update accordingly. >>>>> >>>> >>>> It is a hardware engine which has a firmware to take care of the >>>> managing the frequency request from OS. That is reason to refer it as a >>>> firmware. >>>> >>> >>> Yes I did guess that initially, but I failed to understand when >>> different bindings were posted to deal with devfreq and cpufreq with the >>> same firmware. Ideally if it's the firmware you are talking to, place >>> all these under /firmware node and align all those with single binding. >>> >> >> The OS is not aware of the firmware and OS only knows about the hardware >> engine and has to put forward it's request to the hardware engine using >> the "Perf" state register in both devfreq & cpufreq. So would it be >> still required to put under the /firmware node? >> > > Ah ok, then remove any references to firmware other than stating its > presence in the introduction. E.g. you have "Add cpufreq firmware device > bindings ...". So this is definitely not firmware binding. You are just > presenting the h/w as is and you need to deal with change of firmware in > DT and OS agnostic way. > Sure Sudeep, I will update the references of firmware. >>> Is there anything else that this firmware deals with ? If so all those >>> need to be put in one place. >>> >> >> We deal only with the CPU frequency and L3 frequency(devfreq). >> > > OK > >>>>>> +Properties: >>>>>> +- compatible >>>>>> + Usage: required >>>>>> + Value type: <string> >>>>>> + Definition: must be "qcom,cpufreq-fw". >>>>>> + >>>>>> +* Property qcom,freq-domain >>>>>> +Devices supporting freq-domain must set their "qcom,freq-domain" >>>>>> property with >>>>>> +phandle to a freq_domain_table in their DT node. >>>>>> + >>>>>> +* Frequency Domain Table Node >>>>>> + >>>>>> +This describes the frequency domain belonging to a device. >>>>>> +This node can have following properties: >>>>>> + >>>>>> +- reg >>>>>> + Usage: required >>>>>> + Value type: <prop-encoded-array> >>>>>> + Definition: Addresses and sizes for the memory of the perf >>>>>> + , lut and enable bases. >>>>>> + perf - indicates the base address for the desired >>>>>> + performance state to be set. >>>>>> + lut - indicates the look up table base address for the >>>>>> + cpufreq driver to read frequencies. >>>>>> + enable - indicates the enable register for firmware. >>>>> >>>>> >>>>> You still didn't answer my earlier question. >>>>> >>>>> OS might touch one or 2 registers in lots of IP blocks. I am not sure >>>>> why those are any different from these. Are you trying to align with >>>>> any >>>>> other bindings or specification. Are you trying to make this binding >>>>> generic here ? I understand if it was trying to generalize the firmware >>>>> interface, but you also state it's a hardware engine. So I fail to see >>>>> the need for such specificity here. Why not define the whole IP block >>>>> and the driver knows where to access these specific ones as they are >>>>> specific to this hardware block. In that way if you decide to add more >>>>> data, it's extensible easily without the need for patching DT. >>>>> >>>> >>>> Sorry Sudeep I missed replying to your earlier query. >>>> The High level OS(HLOS) would require to access only these specific >>>> registers from this IP block and just mapping the whole block(huge >>>> region) is unnecessary from the OS point of View. As of now it is a >>>> generic binding for all using this IP block to manage frequency >>>> requests. The OS would only have to know the frequencies supported i.e >>>> to read the lookup table registers and put across the OS request using >>>> the performance state register. >>>> >>> >>> I am not sure if you need to defining bindings to save OSPM IO mapping. >>> In-fact you may be adding more mapping unnecessarily. The mappings are >>> page aligned and spiting the registers and mapping them individually may >>> result in more mappings. >>> >>> I just need to know the rational for such specific choice of registers. >>> I assume it's aligned to some other standard specifications like CPPC >>> though not identical. >>> >> >> I am not sure of the query but there is no other register that the OS is >> required to use other than the ones defined here. >> > > The point is ever IP on the SoC may have 100s to 1000s of registers that > may or may not be used by OS. That's about to the OS to decide and you > just need to provide the hardware view to anyone using the device tree. > It *should not* _just_ represent what you think OS(Linux in particular) > "for now" > >>>>> Eg. Suppose you need some information on power curve for EAS energy >>>>> model, I really hate to update DT for that or even do a mix with DT >>>>> just >>>>> because f/w is no longer modifiable. >>>>> >>>> >>>> For now we are safe. >>>> >>> >>> What do you mean by that ? >> >> I meant here was currently there is no such known case where the f/w is >> no longer modifiable and we need to extend device tree bindings. >> >>> It should be easily extensible is what I am >>> trying to say. You can add more info and alter the information in the >>> driver with compatibles if you keep the register info as minimum as >>> possible. For now, you have enable, set and lut registers. What if you >>> want to provide power numbers ? >>> >> >> Yes I do understand the intent of mapping the whole register space, but >> as per the HW specs these 3 registers would be the only ones required >> for now. I do not think this hardware engine has any information on the >> power numbers. >> > > That's fine. So on this platform DT, will you list only the registers > touched by the OS for all the IP ? I am sure that will not be the case. > Yes, registers list those would be touched by OS only.
On 6/15/2018 5:29 PM, Amit Kucheria wrote: > On Thu, Jun 14, 2018 at 9:24 PM, Taniya Das <tdas@codeaurora.org> wrote: > >>>> Sorry Sudeep I missed replying to your earlier query. >>>> The High level OS(HLOS) would require to access only these specific >>>> registers from this IP block and just mapping the whole block(huge >>>> region) is unnecessary from the OS point of View. As of now it is a >>>> generic binding for all using this IP block to manage frequency >>>> requests. The OS would only have to know the frequencies supported i.e >>>> to read the lookup table registers and put across the OS request using >>>> the performance state register. >>>> >>> >>> I am not sure if you need to defining bindings to save OSPM IO mapping. >>> In-fact you may be adding more mapping unnecessarily. The mappings are >>> page aligned and spiting the registers and mapping them individually may >>> result in more mappings. >>> >>> I just need to know the rational for such specific choice of registers. >>> I assume it's aligned to some other standard specifications like CPPC >>> though not identical. >>> >> >> I am not sure of the query but there is no other register that the OS is >> required to use other than the ones defined here. >> >>>>> Eg. Suppose you need some information on power curve for EAS energy >>>>> model, I really hate to update DT for that or even do a mix with DT just >>>>> because f/w is no longer modifiable. >>>>> >>>> >>>> For now we are safe. >>>> >>> >>> What do you mean by that ? >> >> >> I meant here was currently there is no such known case where the f/w is no >> longer modifiable and we need to extend device tree bindings. >> >>> It should be easily extensible is what I am >>> trying to say. You can add more info and alter the information in the >>> driver with compatibles if you keep the register info as minimum as >>> possible. For now, you have enable, set and lut registers. What if you >>> want to provide power numbers ? >>> >> >> Yes I do understand the intent of mapping the whole register space, but as >> per the HW specs these 3 registers would be the only ones required for now. >> I do not think this hardware engine has any information on the power >> numbers. > > "For now" - I think this is exactly the point that Sudeep is trying to make. > > A future version of the HW engine, or more likely, a firmware > revision, will make more functionality available. Say, this needs > access to another register or two. This will require changing the DT > bindings. Instead, if you map the entire address space, you can just > add offsets to the new registers. > > So in this case, I think you should define the following addresses > (size 0x1400) for the two frequency domains > > 0x17d43000, 0x1400 (power cluster) > 0x17d45800, 0x1400 (perf cluster) > > And in the driver simply add offsets as follows: > > #define ENABLE_OFFSET 0x0 > #define LUT_OFFSET 0x110 > #define PERF_DESIRED_OFFSET 0x920 > The offsets could vary across versions of this IP and that is the reason to provide them through the DT and not define any such offsets. > This will allow you add any new registers in the future w/o modifying > the DT binding and reduce qcom_cpu_resources_init() to a handful of > lines since you no longer need so many OF string matches, and > devm_ioremap()s. > > Regards, > Amit >
On 15/06/18 18:31, Taniya Das wrote: > > > On 6/15/2018 6:53 PM, Sudeep Holla wrote: >> [...] >>> >>>> It should be easily extensible is what I am >>>> trying to say. You can add more info and alter the information in the >>>> driver with compatibles if you keep the register info as minimum as >>>> possible. For now, you have enable, set and lut registers. What if you >>>> want to provide power numbers ? >>>> >>> >>> Yes I do understand the intent of mapping the whole register space, but >>> as per the HW specs these 3 registers would be the only ones required >>> for now. I do not think this hardware engine has any information on the >>> power numbers. >>> >> >> That's fine. So on this platform DT, will you list only the registers >> touched by the OS for all the IP ? I am sure that will not be the case. >> > > Yes, registers list those would be touched by OS only. > You are still missing the point. Look at other IP blocks like pinmux/gpio/...(choose your pick). E.g. Lets say gpio controller driver touches only status set and get registers in a port, will you list then individually in the DT for 'n' ports on the platform ?
On 15/06/18 18:40, Taniya Das wrote: > > > On 6/15/2018 5:29 PM, Amit Kucheria wrote: >> On Thu, Jun 14, 2018 at 9:24 PM, Taniya Das <tdas@codeaurora.org> wrote: >> >>>>> Sorry Sudeep I missed replying to your earlier query. >>>>> The High level OS(HLOS) would require to access only these specific >>>>> registers from this IP block and just mapping the whole block(huge >>>>> region) is unnecessary from the OS point of View. As of now it is a >>>>> generic binding for all using this IP block to manage frequency >>>>> requests. The OS would only have to know the frequencies supported i.e >>>>> to read the lookup table registers and put across the OS request using >>>>> the performance state register. >>>>> >>>> >>>> I am not sure if you need to defining bindings to save OSPM IO mapping. >>>> In-fact you may be adding more mapping unnecessarily. The mappings are >>>> page aligned and spiting the registers and mapping them individually >>>> may >>>> result in more mappings. >>>> >>>> I just need to know the rational for such specific choice of registers. >>>> I assume it's aligned to some other standard specifications like CPPC >>>> though not identical. >>>> >>> >>> I am not sure of the query but there is no other register that the OS is >>> required to use other than the ones defined here. >>> >>>>>> Eg. Suppose you need some information on power curve for EAS energy >>>>>> model, I really hate to update DT for that or even do a mix with >>>>>> DT just >>>>>> because f/w is no longer modifiable. >>>>>> >>>>> >>>>> For now we are safe. >>>>> >>>> >>>> What do you mean by that ? >>> >>> >>> I meant here was currently there is no such known case where the f/w >>> is no >>> longer modifiable and we need to extend device tree bindings. >>> >>>> It should be easily extensible is what I am >>>> trying to say. You can add more info and alter the information in the >>>> driver with compatibles if you keep the register info as minimum as >>>> possible. For now, you have enable, set and lut registers. What if you >>>> want to provide power numbers ? >>>> >>> >>> Yes I do understand the intent of mapping the whole register space, >>> but as >>> per the HW specs these 3 registers would be the only ones required >>> for now. >>> I do not think this hardware engine has any information on the power >>> numbers. >> >> "For now" - I think this is exactly the point that Sudeep is trying to >> make. >> >> A future version of the HW engine, or more likely, a firmware >> revision, will make more functionality available. Say, this needs >> access to another register or two. This will require changing the DT >> bindings. Instead, if you map the entire address space, you can just >> add offsets to the new registers. >> >> So in this case, I think you should define the following addresses >> (size 0x1400) for the two frequency domains >> >> 0x17d43000, 0x1400 (power cluster) >> 0x17d45800, 0x1400 (perf cluster) >> >> And in the driver simply add offsets as follows: >> >> #define ENABLE_OFFSET 0x0 >> #define LUT_OFFSET 0x110 >> #define PERF_DESIRED_OFFSET 0x920 >> > > The offsets could vary across versions of this IP and that is the reason > to provide them through the DT and not define any such offsets. > How many versions do you have and how much has it varied already ? I am now getting a sense that it's mostly decided and fixed my the firmware rather than at the time of hardware design.
On Fri, Jun 15, 2018 at 8:40 PM, Taniya Das <tdas@codeaurora.org> wrote: > > > On 6/15/2018 5:29 PM, Amit Kucheria wrote: >> >> On Thu, Jun 14, 2018 at 9:24 PM, Taniya Das <tdas@codeaurora.org> wrote: >> >>>>> Sorry Sudeep I missed replying to your earlier query. >>>>> The High level OS(HLOS) would require to access only these specific >>>>> registers from this IP block and just mapping the whole block(huge >>>>> region) is unnecessary from the OS point of View. As of now it is a >>>>> generic binding for all using this IP block to manage frequency >>>>> requests. The OS would only have to know the frequencies supported i.e >>>>> to read the lookup table registers and put across the OS request using >>>>> the performance state register. >>>>> >>>> >>>> I am not sure if you need to defining bindings to save OSPM IO mapping. >>>> In-fact you may be adding more mapping unnecessarily. The mappings are >>>> page aligned and spiting the registers and mapping them individually may >>>> result in more mappings. >>>> >>>> I just need to know the rational for such specific choice of registers. >>>> I assume it's aligned to some other standard specifications like CPPC >>>> though not identical. >>>> >>> >>> I am not sure of the query but there is no other register that the OS is >>> required to use other than the ones defined here. >>> >>>>>> Eg. Suppose you need some information on power curve for EAS energy >>>>>> model, I really hate to update DT for that or even do a mix with DT >>>>>> just >>>>>> because f/w is no longer modifiable. >>>>>> >>>>> >>>>> For now we are safe. >>>>> >>>> >>>> What do you mean by that ? >>> >>> >>> >>> I meant here was currently there is no such known case where the f/w is >>> no >>> longer modifiable and we need to extend device tree bindings. >>> >>>> It should be easily extensible is what I am >>>> trying to say. You can add more info and alter the information in the >>>> driver with compatibles if you keep the register info as minimum as >>>> possible. For now, you have enable, set and lut registers. What if you >>>> want to provide power numbers ? >>>> >>> >>> Yes I do understand the intent of mapping the whole register space, but >>> as >>> per the HW specs these 3 registers would be the only ones required for >>> now. >>> I do not think this hardware engine has any information on the power >>> numbers. >> >> >> "For now" - I think this is exactly the point that Sudeep is trying to >> make. >> >> A future version of the HW engine, or more likely, a firmware >> revision, will make more functionality available. Say, this needs >> access to another register or two. This will require changing the DT >> bindings. Instead, if you map the entire address space, you can just >> add offsets to the new registers. >> >> So in this case, I think you should define the following addresses >> (size 0x1400) for the two frequency domains >> >> 0x17d43000, 0x1400 (power cluster) >> 0x17d45800, 0x1400 (perf cluster) >> >> And in the driver simply add offsets as follows: >> >> #define ENABLE_OFFSET 0x0 >> #define LUT_OFFSET 0x110 >> #define PERF_DESIRED_OFFSET 0x920 >> > > The offsets could vary across versions of this IP and that is the reason to > provide them through the DT and not define any such offsets. If that is a known fact internally, you should already introduce versioning information in the DT. e.g qcom,cpufreq-fw-v1. This will give you the ability to deal with IP versions across SoC families. We're currently trying to do the same thing for the TSENS IP. Regards, Amit -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 15/06/18 18:40, Taniya Das wrote: > > > On 6/15/2018 5:29 PM, Amit Kucheria wrote: [...] >> A future version of the HW engine, or more likely, a firmware >> revision, will make more functionality available. Say, this needs >> access to another register or two. This will require changing the DT >> bindings. Instead, if you map the entire address space, you can just >> add offsets to the new registers. >> >> So in this case, I think you should define the following addresses >> (size 0x1400) for the two frequency domains >> >> 0x17d43000, 0x1400 (power cluster) >> 0x17d45800, 0x1400 (perf cluster) >> >> And in the driver simply add offsets as follows: >> >> #define ENABLE_OFFSET 0x0 >> #define LUT_OFFSET 0x110 >> #define PERF_DESIRED_OFFSET 0x920 >> > > The offsets could vary across versions of this IP and that is the reason > to provide them through the DT and not define any such offsets. > Just get compatibles to identify the version of the hardware if it can't be probed and detected. Please don't use DT to get the addresses of each register you use in the driver. That's neither scalable nor nice solution to the problem.
On 6/18/2018 2:51 PM, Sudeep Holla wrote: > > > On 15/06/18 18:40, Taniya Das wrote: >> >> >> On 6/15/2018 5:29 PM, Amit Kucheria wrote: > > [...] > >>> A future version of the HW engine, or more likely, a firmware >>> revision, will make more functionality available. Say, this needs >>> access to another register or two. This will require changing the DT >>> bindings. Instead, if you map the entire address space, you can just >>> add offsets to the new registers. >>> >>> So in this case, I think you should define the following addresses >>> (size 0x1400) for the two frequency domains >>> >>> 0x17d43000, 0x1400 (power cluster) >>> 0x17d45800, 0x1400 (perf cluster) >>> >>> And in the driver simply add offsets as follows: >>> >>> #define ENABLE_OFFSET 0x0 >>> #define LUT_OFFSET 0x110 >>> #define PERF_DESIRED_OFFSET 0x920 >>> >> >> The offsets could vary across versions of this IP and that is the reason >> to provide them through the DT and not define any such offsets. >> > > Just get compatibles to identify the version of the hardware if it can't > be probed and detected. Please don't use DT to get the addresses of each > register you use in the driver. That's neither scalable nor nice > solution to the problem. > Hello Sudeep and Amit, Thanks for the comments, I am consolidating the understanding from the other emails in a single one. I understand that you are looking for this IP to map the full region and define offsets according to access them. But I still not sure how do you want this common driver to scale in the cases where the offsets could vary across version change. DT ==== freq-node { reg = < X x_size>; Where X is the start of the IP address. } Driver code (The below representation is just for example). ============= V1 #define ENABLE 0x0 #define LUT_V1 0x110 #define PERF_V1 0x920 V2 #define LUT_V2 0x150 #define PERF_V2 0x980 V3 #define LUT_V3 0x120 .... Do you want me to use "compatible" flag to if (compatible == v1) enable = readl_relaxed(X + LUT_V1); else if (compatible == v2) enable = readl_relaxed(X + LUT_V2); else if (compatible == v3) enable = readl_relaxed(X + LUT_V2); With the current design I do not need such compatible checks and unmap the ones which are not required after probe. Please let me know your comments.
On 19-06-18, 13:23, Taniya Das wrote: > Driver code (The below representation is just for example). > ============= > > V1 > #define ENABLE 0x0 > #define LUT_V1 0x110 > #define PERF_V1 0x920 > > V2 > #define LUT_V2 0x150 > #define PERF_V2 0x980 > > V3 > #define LUT_V3 0x120 > .... > > Do you want me to use "compatible" flag to > > if (compatible == v1) > enable = readl_relaxed(X + LUT_V1); > else if (compatible == v2) > enable = readl_relaxed(X + LUT_V2); > else if (compatible == v3) > enable = readl_relaxed(X + LUT_V2); You can have fields in a struct somewhere like enable_offset, which you can fill based on compatible string only once during probe and then the rest of the code would just do: enable = readl_relaxed(X + struct->enable_offset);
On 19/06/18 08:53, Taniya Das wrote: > > > On 6/18/2018 2:51 PM, Sudeep Holla wrote: >> >> >> On 15/06/18 18:40, Taniya Das wrote: >>> >>> >>> On 6/15/2018 5:29 PM, Amit Kucheria wrote: >> >> [...] >> >>>> A future version of the HW engine, or more likely, a firmware >>>> revision, will make more functionality available. Say, this needs >>>> access to another register or two. This will require changing the DT >>>> bindings. Instead, if you map the entire address space, you can just >>>> add offsets to the new registers. >>>> >>>> So in this case, I think you should define the following addresses >>>> (size 0x1400) for the two frequency domains >>>> >>>> 0x17d43000, 0x1400 (power cluster) >>>> 0x17d45800, 0x1400 (perf cluster) >>>> >>>> And in the driver simply add offsets as follows: >>>> >>>> #define ENABLE_OFFSET 0x0 >>>> #define LUT_OFFSET 0x110 >>>> #define PERF_DESIRED_OFFSET 0x920 >>>> >>> >>> The offsets could vary across versions of this IP and that is the reason >>> to provide them through the DT and not define any such offsets. >>> >> >> Just get compatibles to identify the version of the hardware if it can't >> be probed and detected. Please don't use DT to get the addresses of each >> register you use in the driver. That's neither scalable nor nice >> solution to the problem. >> Hello Sudeep and Amit, > > Thanks for the comments, I am consolidating the understanding from the > other emails in a single one. > > I understand that you are looking for this IP to map the full region and > define offsets according to access them. > > But I still not sure how do you want this common driver to scale in the > cases where the offsets could vary across version change. > There are plenty of drivers that you can look at as example. TBH most of the drivers implementing support for multiple versions of IP do something on the similar lines. > DT > ==== > freq-node { > reg = < X x_size>; Where X is the start of the IP address. > } > > Driver code (The below representation is just for example). > ============= > > V1 > #define ENABLE 0x0 > #define LUT_V1 0x110 > #define PERF_V1 0x920 > > V2 > #define LUT_V2 0x150 > #define PERF_V2 0x980 > > V3 > #define LUT_V3 0x120 > .... > > Do you want me to use "compatible" flag to > > if (compatible == v1) > enable = readl_relaxed(X + LUT_V1); > else if (compatible == v2) > enable = readl_relaxed(X + LUT_V2); > else if (compatible == v3) > enable = readl_relaxed(X + LUT_V2); > These are implementation details. But you should try to use compatibles only in probe and just record the version in some variable or update the offsets in some device specific structure so that you can use that unconditionally for any access you make on that device. > With the current design I do not need such compatible checks and unmap > the ones which are not required after probe. I am not sure what you mean by unmap after probe. > Please let me know your comments. > Please look at some drivers in the Linux tree for examples. Infact there may be few drivers on QCOM SoC itself. What I am suggesting is the normal practice in the drivers and you should see plenty of examples. Since I was looking at some serial port patch, I can say you can have a look at drivers/tty/serial/amba-pl011.c which supports multiple versions from different vendors. I am sure there are many simpler examples but AMBA PL011 just stood out.
On 6/19/2018 3:04 PM, Sudeep Holla wrote: > > > On 19/06/18 08:53, Taniya Das wrote: >> >> >> On 6/18/2018 2:51 PM, Sudeep Holla wrote: >>> >>> >>> On 15/06/18 18:40, Taniya Das wrote: >>>> >>>> >>>> On 6/15/2018 5:29 PM, Amit Kucheria wrote: >>> >>> [...] >>> >>>>> A future version of the HW engine, or more likely, a firmware >>>>> revision, will make more functionality available. Say, this needs >>>>> access to another register or two. This will require changing the DT >>>>> bindings. Instead, if you map the entire address space, you can just >>>>> add offsets to the new registers. >>>>> >>>>> So in this case, I think you should define the following addresses >>>>> (size 0x1400) for the two frequency domains >>>>> >>>>> 0x17d43000, 0x1400 (power cluster) >>>>> 0x17d45800, 0x1400 (perf cluster) >>>>> >>>>> And in the driver simply add offsets as follows: >>>>> >>>>> #define ENABLE_OFFSET 0x0 >>>>> #define LUT_OFFSET 0x110 >>>>> #define PERF_DESIRED_OFFSET 0x920 >>>>> >>>> >>>> The offsets could vary across versions of this IP and that is the reason >>>> to provide them through the DT and not define any such offsets. >>>> >>> >>> Just get compatibles to identify the version of the hardware if it can't >>> be probed and detected. Please don't use DT to get the addresses of each >>> register you use in the driver. That's neither scalable nor nice >>> solution to the problem. >>> Hello Sudeep and Amit, >> >> Thanks for the comments, I am consolidating the understanding from the >> other emails in a single one. >> >> I understand that you are looking for this IP to map the full region and >> define offsets according to access them. >> >> But I still not sure how do you want this common driver to scale in the >> cases where the offsets could vary across version change. >> > > There are plenty of drivers that you can look at as example. TBH most of > the drivers implementing support for multiple versions of IP do > something on the similar lines. > >> DT >> ==== >> freq-node { >> reg = < X x_size>; Where X is the start of the IP address. >> } >> >> Driver code (The below representation is just for example). >> ============= >> >> V1 >> #define ENABLE 0x0 >> #define LUT_V1 0x110 >> #define PERF_V1 0x920 >> >> V2 >> #define LUT_V2 0x150 >> #define PERF_V2 0x980 >> >> V3 >> #define LUT_V3 0x120 >> .... >> >> Do you want me to use "compatible" flag to >> >> if (compatible == v1) >> enable = readl_relaxed(X + LUT_V1); >> else if (compatible == v2) >> enable = readl_relaxed(X + LUT_V2); >> else if (compatible == v3) >> enable = readl_relaxed(X + LUT_V2); >> > > These are implementation details. But you should try to use compatibles > only in probe and just record the version in some variable or update the > offsets in some device specific structure so that you can use that > unconditionally for any access you make on that device. > >> With the current design I do not need such compatible checks and unmap >> the ones which are not required after probe. > > I am not sure what you mean by unmap after probe. > >> Please let me know your comments. >> > > Please look at some drivers in the Linux tree for examples. Infact there > may be few drivers on QCOM SoC itself. What I am suggesting is the normal > practice in the drivers and you should see plenty of examples. Since I > was looking at some serial port patch, I can say you can have a look at > drivers/tty/serial/amba-pl011.c which supports multiple versions from > different vendors. I am sure there are many simpler examples but AMBA PL011 > just stood out. > Thanks Sudeep, let me take a look at the driver to see how I can associate data (offsets) based on compatible.
diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-fw.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-fw.txt new file mode 100644 index 0000000..e3087ec --- /dev/null +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-fw.txt @@ -0,0 +1,173 @@ +Qualcomm Technologies, Inc. CPUFREQ Bindings + +CPUFREQ FW is a hardware engine used by some Qualcomm Technologies, Inc. (QTI) +SoCs to manage frequency in hardware. It is capable of controlling frequency +for multiple clusters. + +Properties: +- compatible + Usage: required + Value type: <string> + Definition: must be "qcom,cpufreq-fw". + +* Property qcom,freq-domain +Devices supporting freq-domain must set their "qcom,freq-domain" property with +phandle to a freq_domain_table in their DT node. + +* Frequency Domain Table Node + +This describes the frequency domain belonging to a device. +This node can have following properties: + +- reg + Usage: required + Value type: <prop-encoded-array> + Definition: Addresses and sizes for the memory of the perf + , lut and enable bases. + perf - indicates the base address for the desired + performance state to be set. + lut - indicates the look up table base address for the + cpufreq driver to read frequencies. + enable - indicates the enable register for firmware. +- reg-names + Usage: required + Value type: <stringlist> + Definition: Address names. Must be "perf", "lut", "enable". + Must be specified in the same order as the reg property. + +Example: + +Example 1: Dual-cluster, Quad-core per cluster. CPUs within a cluster switch +DCVS state together. + +/ { + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + qcom,freq-domain = <&freq_domain_table0>; + L2_0: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + L3_0: l3-cache { + compatible = "cache"; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&L2_100>; + qcom,freq-domain = <&freq_domain_table0>; + L2_100: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x200>; + enable-method = "psci"; + next-level-cache = <&L2_200>; + qcom,freq-domain = <&freq_domain_table0>; + L2_200: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x300>; + enable-method = "psci"; + next-level-cache = <&L2_300>; + qcom,freq-domain = <&freq_domain_table0>; + L2_300: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x400>; + enable-method = "psci"; + next-level-cache = <&L2_400>; + qcom,freq-domain = <&freq_domain_table1>; + L2_400: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x500>; + enable-method = "psci"; + next-level-cache = <&L2_500>; + qcom,freq-domain = <&freq_domain_table1>; + L2_500: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x600>; + enable-method = "psci"; + next-level-cache = <&L2_600>; + qcom,freq-domain = <&freq_domain_table1>; + L2_600: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x700>; + enable-method = "psci"; + next-level-cache = <&L2_700>; + qcom,freq-domain = <&freq_domain_table1>; + L2_700: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + }; + + qcom,cpufreq-fw { + compatible = "qcom,cpufreq-fw"; + + #address-cells = <1>; + #size-cells = <1>; + + freq_domain_table0 : freq_table0 { + reg = <0x17d43920 0x4>, <0x17d43110 0x500>, + <0x17d41000 0x4>; + reg-names = "perf", "lut", "enable"; + }; + + freq_domain_table1 : freq_table1 { + reg = <0x17d46120 0x4>, <0x17d45910 0x500>, + <0x17d45800 0x4> ; + reg-names = "perf", "lut", "enable"; + }; + };
Add QCOM cpufreq firmware device bindings for Qualcomm Technology Inc's SoCs. This is required for managing the cpu frequency transitions which are controlled by firmware. Signed-off-by: Taniya Das <tdas@codeaurora.org> --- .../bindings/cpufreq/cpufreq-qcom-fw.txt | 173 +++++++++++++++++++++ 1 file changed, 173 insertions(+) create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-fw.txt