| Message ID | 1528851463-21140-4-git-send-email-ricardo.neri-calderon@linux.intel.com |
|---|---|
| State | Not Applicable |
| Delegated to: | David Miller |
| Headers | show |
| Series | Implement an HPET-based hardlockup detector | expand |
On Tue, Jun 12, 2018 at 05:57:23PM -0700, Ricardo Neri wrote: > diff --git a/include/linux/interrupt.h b/include/linux/interrupt.h > index 5426627..dbc5e02 100644 > --- a/include/linux/interrupt.h > +++ b/include/linux/interrupt.h > @@ -61,6 +61,8 @@ > * interrupt handler after suspending interrupts. For system > * wakeup devices users need to implement wakeup detection in > * their interrupt handlers. > + * IRQF_DELIVER_AS_NMI - Configure interrupt to be delivered as non-maskable, if > + * supported by the chip. > */ NAK on the first 6 patches. You really _REALLY_ don't want to expose NMIs to this level. -- To unsubscribe from this list: send the line "unsubscribe sparclinux" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi Peter, Ricardo, On 13/06/18 09:34, Peter Zijlstra wrote: > On Tue, Jun 12, 2018 at 05:57:23PM -0700, Ricardo Neri wrote: >> diff --git a/include/linux/interrupt.h b/include/linux/interrupt.h >> index 5426627..dbc5e02 100644 >> --- a/include/linux/interrupt.h >> +++ b/include/linux/interrupt.h >> @@ -61,6 +61,8 @@ >> * interrupt handler after suspending interrupts. For system >> * wakeup devices users need to implement wakeup detection in >> * their interrupt handlers. >> + * IRQF_DELIVER_AS_NMI - Configure interrupt to be delivered as non-maskable, if >> + * supported by the chip. >> */ > > NAK on the first 6 patches. You really _REALLY_ don't want to expose > NMIs to this level. > I've been working on something similar on arm64 side, and effectively the one thing that might be common to arm64 and intel is the interface to set an interrupt as NMI. So I guess it would be nice to agree on the right approach for this. The way I did it was by introducing a new irq_state and let the irqchip driver handle most of the work (if it supports that state): https://lkml.org/lkml/2018/5/25/181 This has not been ACKed nor NAKed. So I am just asking whether this is a more suitable approach, and if not, is there any suggestions on how to do this? Thanks,
On Wed, 13 Jun 2018, Julien Thierry wrote: > On 13/06/18 09:34, Peter Zijlstra wrote: > > On Tue, Jun 12, 2018 at 05:57:23PM -0700, Ricardo Neri wrote: > > > diff --git a/include/linux/interrupt.h b/include/linux/interrupt.h > > > index 5426627..dbc5e02 100644 > > > --- a/include/linux/interrupt.h > > > +++ b/include/linux/interrupt.h > > > @@ -61,6 +61,8 @@ > > > * interrupt handler after suspending interrupts. For > > > system > > > * wakeup devices users need to implement wakeup > > > detection in > > > * their interrupt handlers. > > > + * IRQF_DELIVER_AS_NMI - Configure interrupt to be delivered as > > > non-maskable, if > > > + * supported by the chip. > > > */ > > > > NAK on the first 6 patches. You really _REALLY_ don't want to expose > > NMIs to this level. > > > > I've been working on something similar on arm64 side, and effectively the one > thing that might be common to arm64 and intel is the interface to set an > interrupt as NMI. So I guess it would be nice to agree on the right approach > for this. > > The way I did it was by introducing a new irq_state and let the irqchip driver > handle most of the work (if it supports that state): > > https://lkml.org/lkml/2018/5/25/181 > > This has not been ACKed nor NAKed. So I am just asking whether this is a more > suitable approach, and if not, is there any suggestions on how to do this? I really didn't pay attention to that as it's burried in the GIC/ARM series which is usually Marc's playground. Adding NMI delivery support at low level architecture irq chip level is perfectly fine, but the exposure of that needs to be restricted very much. Adding it to the generic interrupt control interfaces is not going to happen. That's doomed to begin with and a complete abuse of the interface as the handler can not ever be used for that. Thanks, tglx -- To unsubscribe from this list: send the line "unsubscribe sparclinux" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 13/06/18 10:20, Thomas Gleixner wrote: > On Wed, 13 Jun 2018, Julien Thierry wrote: >> On 13/06/18 09:34, Peter Zijlstra wrote: >>> On Tue, Jun 12, 2018 at 05:57:23PM -0700, Ricardo Neri wrote: >>>> diff --git a/include/linux/interrupt.h b/include/linux/interrupt.h >>>> index 5426627..dbc5e02 100644 >>>> --- a/include/linux/interrupt.h >>>> +++ b/include/linux/interrupt.h >>>> @@ -61,6 +61,8 @@ >>>> * interrupt handler after suspending interrupts. For >>>> system >>>> * wakeup devices users need to implement wakeup >>>> detection in >>>> * their interrupt handlers. >>>> + * IRQF_DELIVER_AS_NMI - Configure interrupt to be delivered as >>>> non-maskable, if >>>> + * supported by the chip. >>>> */ >>> >>> NAK on the first 6 patches. You really _REALLY_ don't want to expose >>> NMIs to this level. >>> >> >> I've been working on something similar on arm64 side, and effectively the one >> thing that might be common to arm64 and intel is the interface to set an >> interrupt as NMI. So I guess it would be nice to agree on the right approach >> for this. >> >> The way I did it was by introducing a new irq_state and let the irqchip driver >> handle most of the work (if it supports that state): >> >> https://lkml.org/lkml/2018/5/25/181 >> >> This has not been ACKed nor NAKed. So I am just asking whether this is a more >> suitable approach, and if not, is there any suggestions on how to do this? > > I really didn't pay attention to that as it's burried in the GIC/ARM series > which is usually Marc's playground. > > Adding NMI delivery support at low level architecture irq chip level is > perfectly fine, but the exposure of that needs to be restricted very > much. Adding it to the generic interrupt control interfaces is not going to > happen. That's doomed to begin with and a complete abuse of the interface > as the handler can not ever be used for that. > Understood, however the need would be to provide a way for a driver to request an interrupt to be delivered as an NMI (if irqchip supports it). But from your response this would be out of the question (in the interrupt/irq/irqchip definitions). Or somehow the concerned irqchip informs the arch it supports NMI delivery and it is up to the interested drivers to query the arch whether NMI delivery is supported by the system? Thanks,
On 13/06/18 10:36, Julien Thierry wrote: > > > On 13/06/18 10:20, Thomas Gleixner wrote: >> On Wed, 13 Jun 2018, Julien Thierry wrote: >>> On 13/06/18 09:34, Peter Zijlstra wrote: >>>> On Tue, Jun 12, 2018 at 05:57:23PM -0700, Ricardo Neri wrote: >>>>> diff --git a/include/linux/interrupt.h b/include/linux/interrupt.h >>>>> index 5426627..dbc5e02 100644 >>>>> --- a/include/linux/interrupt.h >>>>> +++ b/include/linux/interrupt.h >>>>> @@ -61,6 +61,8 @@ >>>>> * interrupt handler after suspending interrupts. >>>>> For >>>>> system >>>>> * wakeup devices users need to implement wakeup >>>>> detection in >>>>> * their interrupt handlers. >>>>> + * IRQF_DELIVER_AS_NMI - Configure interrupt to be delivered as >>>>> non-maskable, if >>>>> + * supported by the chip. >>>>> */ >>>> >>>> NAK on the first 6 patches. You really _REALLY_ don't want to expose >>>> NMIs to this level. >>>> >>> >>> I've been working on something similar on arm64 side, and effectively >>> the one >>> thing that might be common to arm64 and intel is the interface to set an >>> interrupt as NMI. So I guess it would be nice to agree on the right >>> approach >>> for this. >>> >>> The way I did it was by introducing a new irq_state and let the >>> irqchip driver >>> handle most of the work (if it supports that state): >>> >>> https://lkml.org/lkml/2018/5/25/181 >>> >>> This has not been ACKed nor NAKed. So I am just asking whether this >>> is a more >>> suitable approach, and if not, is there any suggestions on how to do >>> this? >> >> I really didn't pay attention to that as it's burried in the GIC/ARM >> series >> which is usually Marc's playground. >> >> Adding NMI delivery support at low level architecture irq chip level is >> perfectly fine, but the exposure of that needs to be restricted very >> much. Adding it to the generic interrupt control interfaces is not >> going to >> happen. That's doomed to begin with and a complete abuse of the interface >> as the handler can not ever be used for that. >> > > Understood, however the need would be to provide a way for a driver to > request an interrupt to be delivered as an NMI (if irqchip supports it). > > But from your response this would be out of the question (in the > interrupt/irq/irqchip definitions). > > Or somehow the concerned irqchip informs the arch it supports NMI > delivery and it is up to the interested drivers to query the arch > whether NMI delivery is supported by the system? Actually scratch that last part, it is also missing a way for the driver to actually communicate to the irqchip that its interrupt should be treated as an NMI, so it wouldn't work...
On Wed, 13 Jun 2018, Julien Thierry wrote: > On 13/06/18 10:20, Thomas Gleixner wrote: > > Adding NMI delivery support at low level architecture irq chip level is > > perfectly fine, but the exposure of that needs to be restricted very > > much. Adding it to the generic interrupt control interfaces is not going to > > happen. That's doomed to begin with and a complete abuse of the interface > > as the handler can not ever be used for that. > > > > Understood, however the need would be to provide a way for a driver to request > an interrupt to be delivered as an NMI (if irqchip supports it). s/driver/specialized code written by people who know what they are doing/ > But from your response this would be out of the question (in the > interrupt/irq/irqchip definitions). Adding some magic to the irq chip is fine, because that's where the low level integration needs to be done, but exposing it through the generic interrupt subsystem is a NONO for obvious reasons. > Or somehow the concerned irqchip informs the arch it supports NMI delivery and > it is up to the interested drivers to query the arch whether NMI delivery is > supported by the system? Yes, we need some infrastructure for that, but that needs to be separate and with very limited exposure. Thanks, tglx -- To unsubscribe from this list: send the line "unsubscribe sparclinux" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 13/06/18 10:20, Thomas Gleixner wrote: > On Wed, 13 Jun 2018, Julien Thierry wrote: >> On 13/06/18 09:34, Peter Zijlstra wrote: >>> On Tue, Jun 12, 2018 at 05:57:23PM -0700, Ricardo Neri wrote: >>>> diff --git a/include/linux/interrupt.h b/include/linux/interrupt.h >>>> index 5426627..dbc5e02 100644 >>>> --- a/include/linux/interrupt.h >>>> +++ b/include/linux/interrupt.h >>>> @@ -61,6 +61,8 @@ >>>> * interrupt handler after suspending interrupts. For >>>> system >>>> * wakeup devices users need to implement wakeup >>>> detection in >>>> * their interrupt handlers. >>>> + * IRQF_DELIVER_AS_NMI - Configure interrupt to be delivered as >>>> non-maskable, if >>>> + * supported by the chip. >>>> */ >>> >>> NAK on the first 6 patches. You really _REALLY_ don't want to expose >>> NMIs to this level. >>> >> >> I've been working on something similar on arm64 side, and effectively the one >> thing that might be common to arm64 and intel is the interface to set an >> interrupt as NMI. So I guess it would be nice to agree on the right approach >> for this. >> >> The way I did it was by introducing a new irq_state and let the irqchip driver >> handle most of the work (if it supports that state): >> >> https://lkml.org/lkml/2018/5/25/181 >> >> This has not been ACKed nor NAKed. So I am just asking whether this is a more >> suitable approach, and if not, is there any suggestions on how to do this? > > I really didn't pay attention to that as it's burried in the GIC/ARM series > which is usually Marc's playground. I'm working my way through it ATM now that I have some brain cycles back. > Adding NMI delivery support at low level architecture irq chip level is > perfectly fine, but the exposure of that needs to be restricted very > much. Adding it to the generic interrupt control interfaces is not going to > happen. That's doomed to begin with and a complete abuse of the interface > as the handler can not ever be used for that. I can only agree with that. Allowing random driver to use request_irq() to make anything an NMI ultimately turns it into a complete mess ("hey, NMI is *faster*, let's use that"), and a potential source of horrible deadlocks. What I'd find more palatable is a way for an irqchip to be able to prioritize some interrupts based on a set of architecturally-defined requirements, and a separate NMI requesting/handling framework that is separate from the IRQ API, as the overall requirements are likely to completely different. It shouldn't have to be nearly as complex as the IRQ API, and require much stricter requirements in terms of what you can do there (flow handling should definitely be different). Thanks, M.
On 13/06/18 10:57, Thomas Gleixner wrote: > On Wed, 13 Jun 2018, Julien Thierry wrote: >> On 13/06/18 10:20, Thomas Gleixner wrote: >>> Adding NMI delivery support at low level architecture irq chip level is >>> perfectly fine, but the exposure of that needs to be restricted very >>> much. Adding it to the generic interrupt control interfaces is not going to >>> happen. That's doomed to begin with and a complete abuse of the interface >>> as the handler can not ever be used for that. >>> >> >> Understood, however the need would be to provide a way for a driver to request >> an interrupt to be delivered as an NMI (if irqchip supports it). > > s/driver/specialized code written by people who know what they are doing/ > >> But from your response this would be out of the question (in the >> interrupt/irq/irqchip definitions). > > Adding some magic to the irq chip is fine, because that's where the low > level integration needs to be done, but exposing it through the generic > interrupt subsystem is a NONO for obvious reasons. > >> Or somehow the concerned irqchip informs the arch it supports NMI delivery and >> it is up to the interested drivers to query the arch whether NMI delivery is >> supported by the system? > > Yes, we need some infrastructure for that, but that needs to be separate > and with very limited exposure. > Right, makes sense. I'll check with Marc how such an infrastructure should be introduced. Thanks,
On Wed, Jun 13, 2018 at 11:06:25AM +0100, Marc Zyngier wrote: > On 13/06/18 10:20, Thomas Gleixner wrote: > > On Wed, 13 Jun 2018, Julien Thierry wrote: > >> On 13/06/18 09:34, Peter Zijlstra wrote: > >>> On Tue, Jun 12, 2018 at 05:57:23PM -0700, Ricardo Neri wrote: > >>>> diff --git a/include/linux/interrupt.h b/include/linux/interrupt.h > >>>> index 5426627..dbc5e02 100644 > >>>> --- a/include/linux/interrupt.h > >>>> +++ b/include/linux/interrupt.h > >>>> @@ -61,6 +61,8 @@ > >>>> * interrupt handler after suspending interrupts. For > >>>> system > >>>> * wakeup devices users need to implement wakeup > >>>> detection in > >>>> * their interrupt handlers. > >>>> + * IRQF_DELIVER_AS_NMI - Configure interrupt to be delivered as > >>>> non-maskable, if > >>>> + * supported by the chip. > >>>> */ > >>> > >>> NAK on the first 6 patches. You really _REALLY_ don't want to expose > >>> NMIs to this level. > >>> > >> > >> I've been working on something similar on arm64 side, and effectively the one > >> thing that might be common to arm64 and intel is the interface to set an > >> interrupt as NMI. So I guess it would be nice to agree on the right approach > >> for this. > >> > >> The way I did it was by introducing a new irq_state and let the irqchip driver > >> handle most of the work (if it supports that state): > >> > >> https://lkml.org/lkml/2018/5/25/181 > >> > >> This has not been ACKed nor NAKed. So I am just asking whether this is a more > >> suitable approach, and if not, is there any suggestions on how to do this? > > > > I really didn't pay attention to that as it's burried in the GIC/ARM series > > which is usually Marc's playground. > > I'm working my way through it ATM now that I have some brain cycles back. > > > Adding NMI delivery support at low level architecture irq chip level is > > perfectly fine, but the exposure of that needs to be restricted very > > much. Adding it to the generic interrupt control interfaces is not going to > > happen. That's doomed to begin with and a complete abuse of the interface > > as the handler can not ever be used for that. > > I can only agree with that. Allowing random driver to use request_irq() > to make anything an NMI ultimately turns it into a complete mess ("hey, > NMI is *faster*, let's use that"), and a potential source of horrible > deadlocks. > > What I'd find more palatable is a way for an irqchip to be able to > prioritize some interrupts based on a set of architecturally-defined > requirements, and a separate NMI requesting/handling framework that is > separate from the IRQ API, as the overall requirements are likely to > completely different. > > It shouldn't have to be nearly as complex as the IRQ API, and require > much stricter requirements in terms of what you can do there (flow > handling should definitely be different). Marc, Julien, do you plan to actively work on this? Would you mind keeping me in the loop? I also need this work for this watchdog. In the meantime, I will go through Julien's patches and try to adapt it to my work. Thanks and BR, Ricardo -- To unsubscribe from this list: send the line "unsubscribe sparclinux" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi Ricardo, On 15/06/18 03:12, Ricardo Neri wrote: > On Wed, Jun 13, 2018 at 11:06:25AM +0100, Marc Zyngier wrote: >> On 13/06/18 10:20, Thomas Gleixner wrote: >>> On Wed, 13 Jun 2018, Julien Thierry wrote: >>>> On 13/06/18 09:34, Peter Zijlstra wrote: >>>>> On Tue, Jun 12, 2018 at 05:57:23PM -0700, Ricardo Neri wrote: >>>>>> diff --git a/include/linux/interrupt.h b/include/linux/interrupt.h >>>>>> index 5426627..dbc5e02 100644 >>>>>> --- a/include/linux/interrupt.h >>>>>> +++ b/include/linux/interrupt.h >>>>>> @@ -61,6 +61,8 @@ >>>>>> * interrupt handler after suspending interrupts. For >>>>>> system >>>>>> * wakeup devices users need to implement wakeup >>>>>> detection in >>>>>> * their interrupt handlers. >>>>>> + * IRQF_DELIVER_AS_NMI - Configure interrupt to be delivered as >>>>>> non-maskable, if >>>>>> + * supported by the chip. >>>>>> */ >>>>> >>>>> NAK on the first 6 patches. You really _REALLY_ don't want to expose >>>>> NMIs to this level. >>>>> >>>> >>>> I've been working on something similar on arm64 side, and effectively the one >>>> thing that might be common to arm64 and intel is the interface to set an >>>> interrupt as NMI. So I guess it would be nice to agree on the right approach >>>> for this. >>>> >>>> The way I did it was by introducing a new irq_state and let the irqchip driver >>>> handle most of the work (if it supports that state): >>>> >>>> https://lkml.org/lkml/2018/5/25/181 >>>> >>>> This has not been ACKed nor NAKed. So I am just asking whether this is a more >>>> suitable approach, and if not, is there any suggestions on how to do this? >>> >>> I really didn't pay attention to that as it's burried in the GIC/ARM series >>> which is usually Marc's playground. >> >> I'm working my way through it ATM now that I have some brain cycles back. >> >>> Adding NMI delivery support at low level architecture irq chip level is >>> perfectly fine, but the exposure of that needs to be restricted very >>> much. Adding it to the generic interrupt control interfaces is not going to >>> happen. That's doomed to begin with and a complete abuse of the interface >>> as the handler can not ever be used for that. >> >> I can only agree with that. Allowing random driver to use request_irq() >> to make anything an NMI ultimately turns it into a complete mess ("hey, >> NMI is *faster*, let's use that"), and a potential source of horrible >> deadlocks. >> >> What I'd find more palatable is a way for an irqchip to be able to >> prioritize some interrupts based on a set of architecturally-defined >> requirements, and a separate NMI requesting/handling framework that is >> separate from the IRQ API, as the overall requirements are likely to >> completely different. >> >> It shouldn't have to be nearly as complex as the IRQ API, and require >> much stricter requirements in terms of what you can do there (flow >> handling should definitely be different). > > Marc, Julien, do you plan to actively work on this? Would you mind keeping > me in the loop? I also need this work for this watchdog. In the meantime, > I will go through Julien's patches and try to adapt it to my work. We are going to work on this and of course your input is most welcome to make sure we have an interface usable across different architectures. In my patches, I'm not sure there is much to adapt to your work as most of it is arch specific (although I wont say no to another pair of eyes looking at them). From what I've seen of your patches, the point where we converge is that need for some code to be able to tell the irqchip "I want that particular interrupt line to be treated/setup as an NMI". We'll make sure to keep you in the loop for discussions/suggestions on this. Thanks,
On Fri, Jun 15, 2018 at 09:01:02AM +0100, Julien Thierry wrote: > Hi Ricardo, > > On 15/06/18 03:12, Ricardo Neri wrote: > >On Wed, Jun 13, 2018 at 11:06:25AM +0100, Marc Zyngier wrote: > >>On 13/06/18 10:20, Thomas Gleixner wrote: > >>>On Wed, 13 Jun 2018, Julien Thierry wrote: > >>>>On 13/06/18 09:34, Peter Zijlstra wrote: > >>>>>On Tue, Jun 12, 2018 at 05:57:23PM -0700, Ricardo Neri wrote: > >>>>>>diff --git a/include/linux/interrupt.h b/include/linux/interrupt.h > >>>>>>index 5426627..dbc5e02 100644 > >>>>>>--- a/include/linux/interrupt.h > >>>>>>+++ b/include/linux/interrupt.h > >>>>>>@@ -61,6 +61,8 @@ > >>>>>> * interrupt handler after suspending interrupts. For > >>>>>>system > >>>>>> * wakeup devices users need to implement wakeup > >>>>>>detection in > >>>>>> * their interrupt handlers. > >>>>>>+ * IRQF_DELIVER_AS_NMI - Configure interrupt to be delivered as > >>>>>>non-maskable, if > >>>>>>+ * supported by the chip. > >>>>>> */ > >>>>> > >>>>>NAK on the first 6 patches. You really _REALLY_ don't want to expose > >>>>>NMIs to this level. > >>>>> > >>>> > >>>>I've been working on something similar on arm64 side, and effectively the one > >>>>thing that might be common to arm64 and intel is the interface to set an > >>>>interrupt as NMI. So I guess it would be nice to agree on the right approach > >>>>for this. > >>>> > >>>>The way I did it was by introducing a new irq_state and let the irqchip driver > >>>>handle most of the work (if it supports that state): > >>>> > >>>>https://lkml.org/lkml/2018/5/25/181 > >>>> > >>>>This has not been ACKed nor NAKed. So I am just asking whether this is a more > >>>>suitable approach, and if not, is there any suggestions on how to do this? > >>> > >>>I really didn't pay attention to that as it's burried in the GIC/ARM series > >>>which is usually Marc's playground. > >> > >>I'm working my way through it ATM now that I have some brain cycles back. > >> > >>>Adding NMI delivery support at low level architecture irq chip level is > >>>perfectly fine, but the exposure of that needs to be restricted very > >>>much. Adding it to the generic interrupt control interfaces is not going to > >>>happen. That's doomed to begin with and a complete abuse of the interface > >>>as the handler can not ever be used for that. > >> > >>I can only agree with that. Allowing random driver to use request_irq() > >>to make anything an NMI ultimately turns it into a complete mess ("hey, > >>NMI is *faster*, let's use that"), and a potential source of horrible > >>deadlocks. > >> > >>What I'd find more palatable is a way for an irqchip to be able to > >>prioritize some interrupts based on a set of architecturally-defined > >>requirements, and a separate NMI requesting/handling framework that is > >>separate from the IRQ API, as the overall requirements are likely to > >>completely different. > >> > >>It shouldn't have to be nearly as complex as the IRQ API, and require > >>much stricter requirements in terms of what you can do there (flow > >>handling should definitely be different). > > > >Marc, Julien, do you plan to actively work on this? Would you mind keeping > >me in the loop? I also need this work for this watchdog. In the meantime, > >I will go through Julien's patches and try to adapt it to my work. > > We are going to work on this and of course your input is most welcome to > make sure we have an interface usable across different architectures. Great! Thanks! I will keep an eye to future version of your "arm64: provide pseudo NMI with GICv3" series. > > In my patches, I'm not sure there is much to adapt to your work as most of > it is arch specific (although I wont say no to another pair of eyes looking > at them). From what I've seen of your patches, the point where we converge > is that need for some code to be able to tell the irqchip "I want that > particular interrupt line to be treated/setup as an NMI". Indeed, there has to be a generic way for the irqchip to announce that it supports configuring an interrupt as NMI... and a way to actually configuring it. > > We'll make sure to keep you in the loop for discussions/suggestions on this. Thank you! Thanks and BR, Ricardo -- To unsubscribe from this list: send the line "unsubscribe sparclinux" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Fri, 15 Jun 2018, Ricardo Neri wrote: > On Fri, Jun 15, 2018 at 09:01:02AM +0100, Julien Thierry wrote: > > In my patches, I'm not sure there is much to adapt to your work as most of > > it is arch specific (although I wont say no to another pair of eyes looking > > at them). From what I've seen of your patches, the point where we converge > > is that need for some code to be able to tell the irqchip "I want that > > particular interrupt line to be treated/setup as an NMI". > > Indeed, there has to be a generic way for the irqchip to announce that it > supports configuring an interrupt as NMI... and a way to actually configuring > it. There has to be nothing. The irqchip infrastructure might be able to provide certain aspects of NMI support, perhaps for initialization, but everything else is fundamentally different and the executional parts simply cannot use any of the irq chip functions at all. Thanks, tglx -- To unsubscribe from this list: send the line "unsubscribe sparclinux" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/include/linux/interrupt.h b/include/linux/interrupt.h index 5426627..dbc5e02 100644 --- a/include/linux/interrupt.h +++ b/include/linux/interrupt.h @@ -61,6 +61,8 @@ * interrupt handler after suspending interrupts. For system * wakeup devices users need to implement wakeup detection in * their interrupt handlers. + * IRQF_DELIVER_AS_NMI - Configure interrupt to be delivered as non-maskable, if + * supported by the chip. */ #define IRQF_SHARED 0x00000080 #define IRQF_PROBE_SHARED 0x00000100 @@ -74,6 +76,7 @@ #define IRQF_NO_THREAD 0x00010000 #define IRQF_EARLY_RESUME 0x00020000 #define IRQF_COND_SUSPEND 0x00040000 +#define IRQF_DELIVER_AS_NMI 0x00080000 #define IRQF_TIMER (__IRQF_TIMER | IRQF_NO_SUSPEND | IRQF_NO_THREAD) diff --git a/include/linux/irq.h b/include/linux/irq.h index 7271a2c..d2520ae 100644 --- a/include/linux/irq.h +++ b/include/linux/irq.h @@ -515,6 +515,8 @@ struct irq_chip { * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip * IRQCHIP_ONESHOT_SAFE: One shot does not require mask/unmask * IRQCHIP_EOI_THREADED: Chip requires eoi() on unmask in threaded mode + * IRQCHIP_CAN_DELIVER_AS_NMI Chip can deliver interrupts it receives as non- + * maskable. */ enum { IRQCHIP_SET_TYPE_MASKED = (1 << 0), @@ -524,6 +526,7 @@ enum { IRQCHIP_SKIP_SET_WAKE = (1 << 4), IRQCHIP_ONESHOT_SAFE = (1 << 5), IRQCHIP_EOI_THREADED = (1 << 6), + IRQCHIP_CAN_DELIVER_AS_NMI = (1 << 7), }; #include <linux/irqdesc.h> diff --git a/kernel/irq/manage.c b/kernel/irq/manage.c index e3336d9..d058aa8 100644 --- a/kernel/irq/manage.c +++ b/kernel/irq/manage.c @@ -1137,7 +1137,7 @@ __setup_irq(unsigned int irq, struct irq_desc *desc, struct irqaction *new) { struct irqaction *old, **old_ptr; unsigned long flags, thread_mask = 0; - int ret, nested, shared = 0; + int ret, nested, shared = 0, deliver_as_nmi = 0; if (!desc) return -EINVAL; @@ -1156,6 +1156,16 @@ __setup_irq(unsigned int irq, struct irq_desc *desc, struct irqaction *new) if (!(new->flags & IRQF_TRIGGER_MASK)) new->flags |= irqd_get_trigger_type(&desc->irq_data); + /* Only deliver as non-maskable interrupt if supported by chip. */ + if (new->flags & IRQF_DELIVER_AS_NMI) { + if (desc->irq_data.chip->flags & IRQCHIP_CAN_DELIVER_AS_NMI) { + irqd_set_deliver_as_nmi(&desc->irq_data); + deliver_as_nmi = 1; + } else { + return -EINVAL; + } + } + /* * Check whether the interrupt nests into another interrupt * thread. @@ -1166,6 +1176,13 @@ __setup_irq(unsigned int irq, struct irq_desc *desc, struct irqaction *new) ret = -EINVAL; goto out_mput; } + + /* Don't allow nesting if interrupt will be delivered as NMI. */ + if (deliver_as_nmi) { + ret = -EINVAL; + goto out_mput; + } + /* * Replace the primary handler which was provided from * the driver for non nested interrupt handling by the @@ -1186,6 +1203,9 @@ __setup_irq(unsigned int irq, struct irq_desc *desc, struct irqaction *new) * thread. */ if (new->thread_fn && !nested) { + if (deliver_as_nmi) + goto out_mput; + ret = setup_irq_thread(new, irq, false); if (ret) goto out_mput;
Certain interrupt controllers (such as APIC) are capable of delivering interrupts as non-maskable. Likewise, drivers or subsystems (e.g., the hardlockup detector) might be interested in requesting a non-maskable interrupt. The new flag IRQF_DELIVER_AS_NMI serves this purpose. When setting up an interrupt, non-maskable delivery will be set in the interrupt state data only if supported by the underlying interrupt controller chips. Interrupt controller chips can declare that they support non-maskable delivery by using the new flag IRQCHIP_CAN_DELIVER_AS_NMI. Cc: Ashok Raj <ashok.raj@intel.com> Cc: Andi Kleen <andi.kleen@intel.com> Cc: Tony Luck <tony.luck@intel.com> Cc: Borislav Petkov <bp@suse.de> Cc: Jacob Pan <jacob.jun.pan@intel.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: "Levin, Alexander (Sasha Levin)" <alexander.levin@verizon.com> Cc: Randy Dunlap <rdunlap@infradead.org> Cc: Masami Hiramatsu <mhiramat@kernel.org> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Bartosz Golaszewski <brgl@bgdev.pl> Cc: Doug Berger <opendmb@gmail.com> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: "Ravi V. Shankar" <ravi.v.shankar@intel.com> Cc: x86@kernel.org Cc: iommu@lists.linux-foundation.org Signed-off-by: Ricardo Neri <ricardo.neri-calderon@linux.intel.com> --- include/linux/interrupt.h | 3 +++ include/linux/irq.h | 3 +++ kernel/irq/manage.c | 22 +++++++++++++++++++++- 3 files changed, 27 insertions(+), 1 deletion(-)