| Message ID | e70e83f07aebaf702fef90a9fac61e41d8b558b0.1526533188.git.hns@goldelico.com |
|---|---|
| State | New |
| Headers | show |
| Series | pcal6524 extensions and fixes for pca953x driver | expand |
On Thu, May 17, 2018 at 6:59 AM, H. Nikolaus Schaller <hns@goldelico.com> wrote: > The register constants are so far defined in a way that they fit > for the pcal9555a when shifted by the number of banks, i.e. are > multiplied by 2 in the accessor function. > > Now, the pcal6524 has 3 banks which means the relative offset > is multiplied by 4 for the standard registers. > > Simply applying the bit shift to the extended registers gives > a wrong result, since the base offset is already included in > the offset. > > Therefore, we have to add code to the 24 bit accessor functions > that adjusts the register number for these exended registers. > > The formula finally used was developed and proposed by > Andy Shevchenko <andy.shevchenko@gmail.com>. > > Suggested-by: Andy Shevchenko <andy.shevchenko@gmail.com> > Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com> Patch applied. Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Thu 2018-05-17 06:59:49, H. Nikolaus Schaller wrote: > The register constants are so far defined in a way that they fit > for the pcal9555a when shifted by the number of banks, i.e. are > multiplied by 2 in the accessor function. > > Now, the pcal6524 has 3 banks which means the relative offset > is multiplied by 4 for the standard registers. > > Simply applying the bit shift to the extended registers gives > a wrong result, since the base offset is already included in > the offset. > > Therefore, we have to add code to the 24 bit accessor functions > that adjusts the register number for these exended registers. > > The formula finally used was developed and proposed by > Andy Shevchenko <andy.shevchenko@gmail.com>. > > Suggested-by: Andy Shevchenko <andy.shevchenko@gmail.com> > Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com> > --- > drivers/gpio/gpio-pca953x.c | 8 ++++++-- > 1 file changed, 6 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c > index c682921d7019..4ad553f4e41f 100644 > --- a/drivers/gpio/gpio-pca953x.c > +++ b/drivers/gpio/gpio-pca953x.c > @@ -222,9 +222,11 @@ static int pca957x_write_regs_16(struct pca953x_chip *chip, int reg, u8 *val) > static int pca953x_write_regs_24(struct pca953x_chip *chip, int reg, u8 *val) > { > int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); > + int addr = (reg & PCAL_GPIO_MASK) << bank_shift; > + int pinctrl = (reg & PCAL_PINCTRL_MASK) << 1; Is this reasonable to do on each register access? Compiler will not be able to optimize out fls and shifts, right? Pavel
On Wed, May 23, 2018 at 5:06 PM, Pavel Machek <pavel@ucw.cz> wrote: > On Thu 2018-05-17 06:59:49, H. Nikolaus Schaller wrote: >> The register constants are so far defined in a way that they fit >> for the pcal9555a when shifted by the number of banks, i.e. are >> multiplied by 2 in the accessor function. >> >> Now, the pcal6524 has 3 banks which means the relative offset >> is multiplied by 4 for the standard registers. >> >> Simply applying the bit shift to the extended registers gives >> a wrong result, since the base offset is already included in >> the offset. >> >> Therefore, we have to add code to the 24 bit accessor functions >> that adjusts the register number for these exended registers. >> >> The formula finally used was developed and proposed by >> Andy Shevchenko <andy.shevchenko@gmail.com>. >> int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); >> + int addr = (reg & PCAL_GPIO_MASK) << bank_shift; >> + int pinctrl = (reg & PCAL_PINCTRL_MASK) << 1; > Is this reasonable to do on each register access? Compiler will not be > able to optimize out fls and shifts, right? On modern CPUs fls() is one assembly command. OTOH, any proposal to do this better? What I can see is that bank_shift is invariant to the function, and maybe cached.
On Tue 2018-06-05 18:37:21, Andy Shevchenko wrote: > On Wed, May 23, 2018 at 5:06 PM, Pavel Machek <pavel@ucw.cz> wrote: > > On Thu 2018-05-17 06:59:49, H. Nikolaus Schaller wrote: > >> The register constants are so far defined in a way that they fit > >> for the pcal9555a when shifted by the number of banks, i.e. are > >> multiplied by 2 in the accessor function. > >> > >> Now, the pcal6524 has 3 banks which means the relative offset > >> is multiplied by 4 for the standard registers. > >> > >> Simply applying the bit shift to the extended registers gives > >> a wrong result, since the base offset is already included in > >> the offset. > >> > >> Therefore, we have to add code to the 24 bit accessor functions > >> that adjusts the register number for these exended registers. > >> > >> The formula finally used was developed and proposed by > >> Andy Shevchenko <andy.shevchenko@gmail.com>. > > >> int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); > >> + int addr = (reg & PCAL_GPIO_MASK) << bank_shift; > >> + int pinctrl = (reg & PCAL_PINCTRL_MASK) << 1; > > > Is this reasonable to do on each register access? Compiler will not be > > able to optimize out fls and shifts, right? > > On modern CPUs fls() is one assembly command. OTOH, any proposal to do > this better? > > What I can see is that bank_shift is invariant to the function, and > maybe cached. Yes, I thought that caching bank_shift might be good idea. I thought it was constant for given chip... Best regards, Pavel
Hi, > Am 05.06.2018 um 22:39 schrieb Pavel Machek <pavel@ucw.cz>: > > On Tue 2018-06-05 18:37:21, Andy Shevchenko wrote: >> On Wed, May 23, 2018 at 5:06 PM, Pavel Machek <pavel@ucw.cz> wrote: >>> On Thu 2018-05-17 06:59:49, H. Nikolaus Schaller wrote: >>>> The register constants are so far defined in a way that they fit >>>> for the pcal9555a when shifted by the number of banks, i.e. are >>>> multiplied by 2 in the accessor function. >>>> >>>> Now, the pcal6524 has 3 banks which means the relative offset >>>> is multiplied by 4 for the standard registers. >>>> >>>> Simply applying the bit shift to the extended registers gives >>>> a wrong result, since the base offset is already included in >>>> the offset. >>>> >>>> Therefore, we have to add code to the 24 bit accessor functions >>>> that adjusts the register number for these exended registers. >>>> >>>> The formula finally used was developed and proposed by >>>> Andy Shevchenko <andy.shevchenko@gmail.com>. >> >>>> int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); >>>> + int addr = (reg & PCAL_GPIO_MASK) << bank_shift; >>>> + int pinctrl = (reg & PCAL_PINCTRL_MASK) << 1; >> >>> Is this reasonable to do on each register access? Compiler will not be >>> able to optimize out fls and shifts, right? >> >> On modern CPUs fls() is one assembly command. OTOH, any proposal to do >> this better? >> >> What I can see is that bank_shift is invariant to the function, and >> maybe cached. > > Yes, I thought that caching bank_shift might be good idea. I thought > it was constant for given chip... Yes, it is an f(chip), but the question that comes to my mind is if optimization is worth any effort. This is an accessor method over i2c which tends to be slow (100 / 400kHz SCL) compared to the CPU. So saving 1 or 2 CPU cycles here doesn't seem to be a significant improvement. Maybe it is more valuable to improve the code path through the i2c core? BR, Nikolaus -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Wed 2018-06-06 07:33:32, H. Nikolaus Schaller wrote: > Hi, > > > Am 05.06.2018 um 22:39 schrieb Pavel Machek <pavel@ucw.cz>: > > > > On Tue 2018-06-05 18:37:21, Andy Shevchenko wrote: > >> On Wed, May 23, 2018 at 5:06 PM, Pavel Machek <pavel@ucw.cz> wrote: > >>> On Thu 2018-05-17 06:59:49, H. Nikolaus Schaller wrote: > >>>> The register constants are so far defined in a way that they fit > >>>> for the pcal9555a when shifted by the number of banks, i.e. are > >>>> multiplied by 2 in the accessor function. > >>>> > >>>> Now, the pcal6524 has 3 banks which means the relative offset > >>>> is multiplied by 4 for the standard registers. > >>>> > >>>> Simply applying the bit shift to the extended registers gives > >>>> a wrong result, since the base offset is already included in > >>>> the offset. > >>>> > >>>> Therefore, we have to add code to the 24 bit accessor functions > >>>> that adjusts the register number for these exended registers. > >>>> > >>>> The formula finally used was developed and proposed by > >>>> Andy Shevchenko <andy.shevchenko@gmail.com>. > >> > >>>> int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); > >>>> + int addr = (reg & PCAL_GPIO_MASK) << bank_shift; > >>>> + int pinctrl = (reg & PCAL_PINCTRL_MASK) << 1; > >> > >>> Is this reasonable to do on each register access? Compiler will not be > >>> able to optimize out fls and shifts, right? > >> > >> On modern CPUs fls() is one assembly command. OTOH, any proposal to do > >> this better? > >> > >> What I can see is that bank_shift is invariant to the function, and > >> maybe cached. > > > > Yes, I thought that caching bank_shift might be good idea. I thought > > it was constant for given chip... > > Yes, it is an f(chip), but the question that comes to my mind is if > optimization is worth any effort. This is an accessor method over It will also be less ugly. Copy&pasted complex exprepsion all over the driver is not nice. Pavel
diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c index c682921d7019..4ad553f4e41f 100644 --- a/drivers/gpio/gpio-pca953x.c +++ b/drivers/gpio/gpio-pca953x.c @@ -222,9 +222,11 @@ static int pca957x_write_regs_16(struct pca953x_chip *chip, int reg, u8 *val) static int pca953x_write_regs_24(struct pca953x_chip *chip, int reg, u8 *val) { int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); + int addr = (reg & PCAL_GPIO_MASK) << bank_shift; + int pinctrl = (reg & PCAL_PINCTRL_MASK) << 1; return i2c_smbus_write_i2c_block_data(chip->client, - (reg << bank_shift) | REG_ADDR_AI, + pinctrl | addr | REG_ADDR_AI, NBANK(chip), val); } @@ -264,9 +266,11 @@ static int pca953x_read_regs_16(struct pca953x_chip *chip, int reg, u8 *val) static int pca953x_read_regs_24(struct pca953x_chip *chip, int reg, u8 *val) { int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); + int addr = (reg & PCAL_GPIO_MASK) << bank_shift; + int pinctrl = (reg & PCAL_PINCTRL_MASK) << 1; return i2c_smbus_read_i2c_block_data(chip->client, - (reg << bank_shift) | REG_ADDR_AI, + pinctrl | addr | REG_ADDR_AI, NBANK(chip), val); }
The register constants are so far defined in a way that they fit for the pcal9555a when shifted by the number of banks, i.e. are multiplied by 2 in the accessor function. Now, the pcal6524 has 3 banks which means the relative offset is multiplied by 4 for the standard registers. Simply applying the bit shift to the extended registers gives a wrong result, since the base offset is already included in the offset. Therefore, we have to add code to the 24 bit accessor functions that adjusts the register number for these exended registers. The formula finally used was developed and proposed by Andy Shevchenko <andy.shevchenko@gmail.com>. Suggested-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com> --- drivers/gpio/gpio-pca953x.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)