| Message ID | 1526897190-28714-1-git-send-email-Anson.Huang@nxp.com |
|---|---|
| State | New |
| Headers | show |
| Series | gpio: mxc: add clock operation | expand |
Hi Anson,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on gpio/for-next]
[also build test ERROR on v4.17-rc6 next-20180517]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Anson-Huang/gpio-mxc-add-clock-operation/20180522-165520
base: https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio.git for-next
config: arm-multi_v5_defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm
All error/warnings (new ones prefixed by >>):
drivers/gpio/gpio-mxc.c: In function 'mxc_gpio_probe':
>> drivers/gpio/gpio-mxc.c:439:14: error: implicit declaration of function 'devm_clk_get'; did you mean 'devm_kfree'? [-Werror=implicit-function-declaration]
port->clk = devm_clk_get(&pdev->dev, NULL);
^~~~~~~~~~~~
devm_kfree
>> drivers/gpio/gpio-mxc.c:439:12: warning: assignment makes pointer from integer without a cast [-Wint-conversion]
port->clk = devm_clk_get(&pdev->dev, NULL);
^
>> drivers/gpio/gpio-mxc.c:443:8: error: implicit declaration of function 'clk_prepare_enable'; did you mean 'cpu_hotplug_enable'? [-Werror=implicit-function-declaration]
err = clk_prepare_enable(port->clk);
^~~~~~~~~~~~~~~~~~
cpu_hotplug_enable
>> drivers/gpio/gpio-mxc.c:517:2: error: implicit declaration of function 'clk_disable_unprepare' [-Werror=implicit-function-declaration]
clk_disable_unprepare(port->clk);
^~~~~~~~~~~~~~~~~~~~~
cc1: some warnings being treated as errors
vim +439 drivers/gpio/gpio-mxc.c
408
409 static int mxc_gpio_probe(struct platform_device *pdev)
410 {
411 struct device_node *np = pdev->dev.of_node;
412 struct mxc_gpio_port *port;
413 struct resource *iores;
414 int irq_base;
415 int err;
416
417 mxc_gpio_get_hw(pdev);
418
419 port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
420 if (!port)
421 return -ENOMEM;
422
423 port->dev = &pdev->dev;
424
425 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
426 port->base = devm_ioremap_resource(&pdev->dev, iores);
427 if (IS_ERR(port->base))
428 return PTR_ERR(port->base);
429
430 port->irq_high = platform_get_irq(pdev, 1);
431 if (port->irq_high < 0)
432 port->irq_high = 0;
433
434 port->irq = platform_get_irq(pdev, 0);
435 if (port->irq < 0)
436 return port->irq;
437
438 /* the controller clock is optional */
> 439 port->clk = devm_clk_get(&pdev->dev, NULL);
440 if (IS_ERR(port->clk))
441 port->clk = NULL;
442
> 443 err = clk_prepare_enable(port->clk);
444 if (err) {
445 dev_err(&pdev->dev, "Unable to enable clock.\n");
446 return err;
447 }
448
449 /* disable the interrupt and clear the status */
450 writel(0, port->base + GPIO_IMR);
451 writel(~0, port->base + GPIO_ISR);
452
453 if (mxc_gpio_hwtype == IMX21_GPIO) {
454 /*
455 * Setup one handler for all GPIO interrupts. Actually setting
456 * the handler is needed only once, but doing it for every port
457 * is more robust and easier.
458 */
459 irq_set_chained_handler(port->irq, mx2_gpio_irq_handler);
460 } else {
461 /* setup one handler for each entry */
462 irq_set_chained_handler_and_data(port->irq,
463 mx3_gpio_irq_handler, port);
464 if (port->irq_high > 0)
465 /* setup handler for GPIO 16 to 31 */
466 irq_set_chained_handler_and_data(port->irq_high,
467 mx3_gpio_irq_handler,
468 port);
469 }
470
471 err = bgpio_init(&port->gc, &pdev->dev, 4,
472 port->base + GPIO_PSR,
473 port->base + GPIO_DR, NULL,
474 port->base + GPIO_GDIR, NULL,
475 BGPIOF_READ_OUTPUT_REG_SET);
476 if (err)
477 goto out_bgio;
478
479 if (of_property_read_bool(np, "gpio-ranges")) {
480 port->gc.request = gpiochip_generic_request;
481 port->gc.free = gpiochip_generic_free;
482 }
483
484 port->gc.to_irq = mxc_gpio_to_irq;
485 port->gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 :
486 pdev->id * 32;
487
488 err = devm_gpiochip_add_data(&pdev->dev, &port->gc, port);
489 if (err)
490 goto out_bgio;
491
492 irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id());
493 if (irq_base < 0) {
494 err = irq_base;
495 goto out_bgio;
496 }
497
498 port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
499 &irq_domain_simple_ops, NULL);
500 if (!port->domain) {
501 err = -ENODEV;
502 goto out_bgio;
503 }
504
505 /* gpio-mxc can be a generic irq chip */
506 err = mxc_gpio_init_gc(port, irq_base);
507 if (err < 0)
508 goto out_irqdomain_remove;
509
510 list_add_tail(&port->node, &mxc_gpio_ports);
511
512 return 0;
513
514 out_irqdomain_remove:
515 irq_domain_remove(port->domain);
516 out_bgio:
> 517 clk_disable_unprepare(port->clk);
518 dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
519 return err;
520 }
521
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
On Mon, May 21, 2018 at 12:06 PM, Anson Huang <Anson.Huang@nxp.com> wrote: > i.MX6SLL has GPIO clock gates in CCM CCGR, need > to enable them before accessing registers, add > optional clock operation for GPIO driver. > > Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Some warnings from the build robot, seem like a missing #include <linux/clk.h> or something. Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi, Linus Anson Huang Best Regards! > -----Original Message----- > From: Linus Walleij [mailto:linus.walleij@linaro.org] > Sent: Thursday, May 24, 2018 4:13 PM > To: Anson Huang <anson.huang@nxp.com> > Cc: dl-linux-imx <linux-imx@nxp.com>; open list:GPIO SUBSYSTEM > <linux-gpio@vger.kernel.org>; linux-kernel@vger.kernel.org > Subject: Re: [PATCH] gpio: mxc: add clock operation > > On Mon, May 21, 2018 at 12:06 PM, Anson Huang <Anson.Huang@nxp.com> > wrote: > > > i.MX6SLL has GPIO clock gates in CCM CCGR, need to enable them before > > accessing registers, add optional clock operation for GPIO driver. > > > > Signed-off-by: Anson Huang <Anson.Huang@nxp.com> > > Some warnings from the build robot, seem like a missing #include <linux/clk.h> > or something. Please ignore this patch, the "[PATCH V3] gpio: mxc: add clock operation" is to fix this build warning. Thanks. Anson. > > Yours, > Linus Walleij
diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c index 11ec722..8fc37c4 100644 --- a/drivers/gpio/gpio-mxc.c +++ b/drivers/gpio/gpio-mxc.c @@ -60,6 +60,7 @@ struct mxc_gpio_hwdata { struct mxc_gpio_port { struct list_head node; void __iomem *base; + struct clk *clk; int irq; int irq_high; struct irq_domain *domain; @@ -434,6 +435,17 @@ static int mxc_gpio_probe(struct platform_device *pdev) if (port->irq < 0) return port->irq; + /* the controller clock is optional */ + port->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(port->clk)) + port->clk = NULL; + + err = clk_prepare_enable(port->clk); + if (err) { + dev_err(&pdev->dev, "Unable to enable clock.\n"); + return err; + } + /* disable the interrupt and clear the status */ writel(0, port->base + GPIO_IMR); writel(~0, port->base + GPIO_ISR); @@ -502,6 +514,7 @@ static int mxc_gpio_probe(struct platform_device *pdev) out_irqdomain_remove: irq_domain_remove(port->domain); out_bgio: + clk_disable_unprepare(port->clk); dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err); return err; }
i.MX6SLL has GPIO clock gates in CCM CCGR, need to enable them before accessing registers, add optional clock operation for GPIO driver. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> --- drivers/gpio/gpio-mxc.c | 13 +++++++++++++ 1 file changed, 13 insertions(+)