| Message ID | 20180516185146.30708-26-edgar.iglesias@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | target-microblaze: Add support for Extended Addressing | expand |
On 05/16/2018 03:51 PM, Edgar E. Iglesias wrote: > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> > > Add explicit handling for MMU_R_TLBX and log accesses to > invalid MMU registers. We can now remove the state for > all regs but PID, ZPR and TLBX (0 - 2). > > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> > --- > target/microblaze/mmu.c | 7 +++++-- > target/microblaze/mmu.h | 2 +- > 2 files changed, 6 insertions(+), 3 deletions(-) > > diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c > index f4a4c339c9..231803ceea 100644 > --- a/target/microblaze/mmu.c > +++ b/target/microblaze/mmu.c > @@ -211,11 +211,14 @@ uint32_t mmu_read(CPUMBState *env, uint32_t rn) > } > r = env->mmu.regs[rn]; > break; > + case MMU_R_TLBX: > + r = env->mmu.regs[rn]; > + break; > case MMU_R_TLBSX: > qemu_log_mask(LOG_GUEST_ERROR, "TLBSX is write-only.\n"); > break; > default: > - r = env->mmu.regs[rn]; > + qemu_log_mask(LOG_GUEST_ERROR, "Invalid MMU register %d.\n", rn); > break; > } > D(qemu_log("%s rn=%d=%x\n", __func__, rn, r)); > @@ -298,7 +301,7 @@ void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v) > break; > } > default: > - env->mmu.regs[rn] = v; I was afraid of an overflow but the only way to reach this function is via dec_msr() which calls with rn &= 7, whew. Lot of magic numbers... > + qemu_log_mask(LOG_GUEST_ERROR, "Invalid MMU register %d.\n", rn); > break; > } > } > diff --git a/target/microblaze/mmu.h b/target/microblaze/mmu.h > index 113539c6e9..624becfded 100644 > --- a/target/microblaze/mmu.h > +++ b/target/microblaze/mmu.h > @@ -67,7 +67,7 @@ struct microblaze_mmu > /* We keep a separate ram for the tids to avoid the 48 bit tag width. */ > uint8_t tids[TLB_ENTRIES]; > /* Control flops. */ > - uint32_t regs[8]; > + uint32_t regs[3]; > > int c_mmu; > int c_mmu_tlb_access; > Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c index f4a4c339c9..231803ceea 100644 --- a/target/microblaze/mmu.c +++ b/target/microblaze/mmu.c @@ -211,11 +211,14 @@ uint32_t mmu_read(CPUMBState *env, uint32_t rn) } r = env->mmu.regs[rn]; break; + case MMU_R_TLBX: + r = env->mmu.regs[rn]; + break; case MMU_R_TLBSX: qemu_log_mask(LOG_GUEST_ERROR, "TLBSX is write-only.\n"); break; default: - r = env->mmu.regs[rn]; + qemu_log_mask(LOG_GUEST_ERROR, "Invalid MMU register %d.\n", rn); break; } D(qemu_log("%s rn=%d=%x\n", __func__, rn, r)); @@ -298,7 +301,7 @@ void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v) break; } default: - env->mmu.regs[rn] = v; + qemu_log_mask(LOG_GUEST_ERROR, "Invalid MMU register %d.\n", rn); break; } } diff --git a/target/microblaze/mmu.h b/target/microblaze/mmu.h index 113539c6e9..624becfded 100644 --- a/target/microblaze/mmu.h +++ b/target/microblaze/mmu.h @@ -67,7 +67,7 @@ struct microblaze_mmu /* We keep a separate ram for the tids to avoid the 48 bit tag width. */ uint8_t tids[TLB_ENTRIES]; /* Control flops. */ - uint32_t regs[8]; + uint32_t regs[3]; int c_mmu; int c_mmu_tlb_access;