| Message ID | 1524144103-21432-4-git-send-email-amelie.delaunay@st.com |
|---|---|
| State | Accepted |
| Headers | show |
| Series | Various fixes on STM32 RTC | expand |
On Thu, Apr 19, 2018 at 03:21:42PM +0200, Amelie Delaunay wrote: > RTC driver should not be aware of the PWR registers offset and bits > position. Furthermore, we can imagine that Disable Backup Protection (DBP) > relative register and bit mask could change depending on the SoC. So this > patch moves st,syscfg property from single pwrcfg phandle to pwrcfg > phandle/offset/mask triplet. > > Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> > --- > Documentation/devicetree/bindings/rtc/st,stm32-rtc.txt | 10 ++++++---- > 1 file changed, 6 insertions(+), 4 deletions(-) > > diff --git a/Documentation/devicetree/bindings/rtc/st,stm32-rtc.txt b/Documentation/devicetree/bindings/rtc/st,stm32-rtc.txt > index a66692a..00f8b5d 100644 > --- a/Documentation/devicetree/bindings/rtc/st,stm32-rtc.txt > +++ b/Documentation/devicetree/bindings/rtc/st,stm32-rtc.txt > @@ -14,8 +14,10 @@ Required properties: > It is required only on stm32h7. > - interrupt-parent: phandle for the interrupt controller. > - interrupts: rtc alarm interrupt. > -- st,syscfg: phandle for pwrcfg, mandatory to disable/enable backup domain > - (RTC registers) write protection. > +- st,syscfg: phandle/offset/mask triplet. The phandle to pwrcfg used to > + access control register at offset, and change the dbp (Disable Backup > + Protection) bit represented by the mask, mandatory to disable/enable backup > + domain (RTC registers) write protection. It's fine to add this, but you are breaking compatibility in the driver with existing DTBs by requiring these new fields. Rob
Amelie, On 26/04/2018 21:58:03-0500, Rob Herring wrote: > On Thu, Apr 19, 2018 at 03:21:42PM +0200, Amelie Delaunay wrote: > > RTC driver should not be aware of the PWR registers offset and bits > > position. Furthermore, we can imagine that Disable Backup Protection (DBP) > > relative register and bit mask could change depending on the SoC. So this > > patch moves st,syscfg property from single pwrcfg phandle to pwrcfg > > phandle/offset/mask triplet. > > > > Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> > > --- > > Documentation/devicetree/bindings/rtc/st,stm32-rtc.txt | 10 ++++++---- > > 1 file changed, 6 insertions(+), 4 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/rtc/st,stm32-rtc.txt b/Documentation/devicetree/bindings/rtc/st,stm32-rtc.txt > > index a66692a..00f8b5d 100644 > > --- a/Documentation/devicetree/bindings/rtc/st,stm32-rtc.txt > > +++ b/Documentation/devicetree/bindings/rtc/st,stm32-rtc.txt > > @@ -14,8 +14,10 @@ Required properties: > > It is required only on stm32h7. > > - interrupt-parent: phandle for the interrupt controller. > > - interrupts: rtc alarm interrupt. > > -- st,syscfg: phandle for pwrcfg, mandatory to disable/enable backup domain > > - (RTC registers) write protection. > > +- st,syscfg: phandle/offset/mask triplet. The phandle to pwrcfg used to > > + access control register at offset, and change the dbp (Disable Backup > > + Protection) bit represented by the mask, mandatory to disable/enable backup > > + domain (RTC registers) write protection. > > It's fine to add this, but you are breaking compatibility in the driver > with existing DTBs by requiring these new fields. > I'm fine with that change but I would like confirmation that this has been well thought. Maybe Maxime or Alexandre could give their ack.
Hi Alexandre, On 05/03/2018 10:53 PM, Alexandre Belloni wrote: > Amelie, > > On 26/04/2018 21:58:03-0500, Rob Herring wrote: >> On Thu, Apr 19, 2018 at 03:21:42PM +0200, Amelie Delaunay wrote: >>> RTC driver should not be aware of the PWR registers offset and bits >>> position. Furthermore, we can imagine that Disable Backup Protection (DBP) >>> relative register and bit mask could change depending on the SoC. So this >>> patch moves st,syscfg property from single pwrcfg phandle to pwrcfg >>> phandle/offset/mask triplet. >>> >>> Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> >>> --- >>> Documentation/devicetree/bindings/rtc/st,stm32-rtc.txt | 10 ++++++---- >>> 1 file changed, 6 insertions(+), 4 deletions(-) >>> >>> diff --git a/Documentation/devicetree/bindings/rtc/st,stm32-rtc.txt b/Documentation/devicetree/bindings/rtc/st,stm32-rtc.txt >>> index a66692a..00f8b5d 100644 >>> --- a/Documentation/devicetree/bindings/rtc/st,stm32-rtc.txt >>> +++ b/Documentation/devicetree/bindings/rtc/st,stm32-rtc.txt >>> @@ -14,8 +14,10 @@ Required properties: >>> It is required only on stm32h7. >>> - interrupt-parent: phandle for the interrupt controller. >>> - interrupts: rtc alarm interrupt. >>> -- st,syscfg: phandle for pwrcfg, mandatory to disable/enable backup domain >>> - (RTC registers) write protection. >>> +- st,syscfg: phandle/offset/mask triplet. The phandle to pwrcfg used to >>> + access control register at offset, and change the dbp (Disable Backup >>> + Protection) bit represented by the mask, mandatory to disable/enable backup >>> + domain (RTC registers) write protection. >> >> It's fine to add this, but you are breaking compatibility in the driver >> with existing DTBs by requiring these new fields. >> > > I'm fine with that change but I would like confirmation that this has > been well thought. Maybe Maxime or Alexandre could give their ack. > It's a good thing to remove PWR registers information from RTC driver. My only concern was the compatibility with old DT but we can accept it. Indeed, Kernel will continue to boot fine, only RTC will not probe if we use old DT. Acked-by: Alexandre TORGUE <alexandre.torgue@st.com> Regards alex
Hi, On 05/04/2018 09:40 AM, Alexandre Torgue wrote: > Hi Alexandre, > > On 05/03/2018 10:53 PM, Alexandre Belloni wrote: >> Amelie, >> >> On 26/04/2018 21:58:03-0500, Rob Herring wrote: >>> On Thu, Apr 19, 2018 at 03:21:42PM +0200, Amelie Delaunay wrote: >>>> RTC driver should not be aware of the PWR registers offset and bits >>>> position. Furthermore, we can imagine that Disable Backup Protection >>>> (DBP) >>>> relative register and bit mask could change depending on the SoC. So >>>> this >>>> patch moves st,syscfg property from single pwrcfg phandle to pwrcfg >>>> phandle/offset/mask triplet. >>>> >>>> Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> >>>> --- >>>> Documentation/devicetree/bindings/rtc/st,stm32-rtc.txt | 10 >>>> ++++++---- >>>> 1 file changed, 6 insertions(+), 4 deletions(-) >>>> >>>> diff --git a/Documentation/devicetree/bindings/rtc/st,stm32-rtc.txt >>>> b/Documentation/devicetree/bindings/rtc/st,stm32-rtc.txt >>>> index a66692a..00f8b5d 100644 >>>> --- a/Documentation/devicetree/bindings/rtc/st,stm32-rtc.txt >>>> +++ b/Documentation/devicetree/bindings/rtc/st,stm32-rtc.txt >>>> @@ -14,8 +14,10 @@ Required properties: >>>> It is required only on stm32h7. >>>> - interrupt-parent: phandle for the interrupt controller. >>>> - interrupts: rtc alarm interrupt. >>>> -- st,syscfg: phandle for pwrcfg, mandatory to disable/enable backup >>>> domain >>>> - (RTC registers) write protection. >>>> +- st,syscfg: phandle/offset/mask triplet. The phandle to pwrcfg >>>> used to >>>> + access control register at offset, and change the dbp (Disable >>>> Backup >>>> + Protection) bit represented by the mask, mandatory to >>>> disable/enable backup >>>> + domain (RTC registers) write protection. >>> >>> It's fine to add this, but you are breaking compatibility in the driver >>> with existing DTBs by requiring these new fields. >>> >> >> I'm fine with that change but I would like confirmation that this has >> been well thought. Maybe Maxime or Alexandre could give their ack. >> > > It's a good thing to remove PWR registers information from RTC driver. > My only concern was the compatibility with old DT but we can accept it. > Indeed, Kernel will continue to boot fine, only RTC will not probe if we > use old DT. > > Acked-by: Alexandre TORGUE <alexandre.torgue@st.com> > > Regards > alex I am going to send a series to update st,syscfg property in stm32f429/stm32f746/stm32h743 RTC node. Thanks, Amelie
diff --git a/Documentation/devicetree/bindings/rtc/st,stm32-rtc.txt b/Documentation/devicetree/bindings/rtc/st,stm32-rtc.txt index a66692a..00f8b5d 100644 --- a/Documentation/devicetree/bindings/rtc/st,stm32-rtc.txt +++ b/Documentation/devicetree/bindings/rtc/st,stm32-rtc.txt @@ -14,8 +14,10 @@ Required properties: It is required only on stm32h7. - interrupt-parent: phandle for the interrupt controller. - interrupts: rtc alarm interrupt. -- st,syscfg: phandle for pwrcfg, mandatory to disable/enable backup domain - (RTC registers) write protection. +- st,syscfg: phandle/offset/mask triplet. The phandle to pwrcfg used to + access control register at offset, and change the dbp (Disable Backup + Protection) bit represented by the mask, mandatory to disable/enable backup + domain (RTC registers) write protection. Optional properties (to override default rtc_ck parent clock): - assigned-clocks: reference to the rtc_ck clock entry. @@ -31,7 +33,7 @@ Example: assigned-clock-parents = <&rcc 1 CLK_LSE>; interrupt-parent = <&exti>; interrupts = <17 1>; - st,syscfg = <&pwrcfg>; + st,syscfg = <&pwrcfg 0x00 0x100>; }; rtc: rtc@58004000 { @@ -44,5 +46,5 @@ Example: interrupt-parent = <&exti>; interrupts = <17 1>; interrupt-names = "alarm"; - st,syscfg = <&pwrcfg>; + st,syscfg = <&pwrcfg 0x00 0x100>; };
RTC driver should not be aware of the PWR registers offset and bits position. Furthermore, we can imagine that Disable Backup Protection (DBP) relative register and bit mask could change depending on the SoC. So this patch moves st,syscfg property from single pwrcfg phandle to pwrcfg phandle/offset/mask triplet. Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> --- Documentation/devicetree/bindings/rtc/st,stm32-rtc.txt | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-)