| Message ID | 94a7d3b1240297cd0cac82df52954d0a53d50d36.1520832210.git.chunfeng.yun@mediatek.com |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | None | expand |
On 03/12/2018 06:25 AM, Chunfeng Yun wrote: > Add two properties of ref_clk and coefficient used by U2 slew rate > calibrate which may vary on different SoCs > > Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> > --- > Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt > index 41e09ed..0d34b2b 100644 > --- a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt > +++ b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt > @@ -27,6 +27,10 @@ Optional properties (controller (parent) node): > - reg : offset and length of register shared by multiple ports, > exclude port's private register. It is needed on mt2701 > and mt8173, but not on mt2712. > + - mediatek,src-ref-clk-mhz : frequency of reference clock for slew rate > + calibrate > + - mediatek,src-coef : coefficient for slew rate calibrate, depends on > + SoC process > > Required properties (port (child) node): > - reg : address and length of the register set for the port. > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Wed, 2018-03-14 at 00:21 +0100, Matthias Brugger wrote: > > On 03/12/2018 06:25 AM, Chunfeng Yun wrote: > > Add two properties of ref_clk and coefficient used by U2 slew rate > > calibrate which may vary on different SoCs > > > > Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> > > Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> > Thanks again > > --- > > Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt | 4 ++++ > > 1 file changed, 4 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt > > index 41e09ed..0d34b2b 100644 > > --- a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt > > +++ b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt > > @@ -27,6 +27,10 @@ Optional properties (controller (parent) node): > > - reg : offset and length of register shared by multiple ports, > > exclude port's private register. It is needed on mt2701 > > and mt8173, but not on mt2712. > > + - mediatek,src-ref-clk-mhz : frequency of reference clock for slew rate > > + calibrate > > + - mediatek,src-coef : coefficient for slew rate calibrate, depends on > > + SoC process > > > > Required properties (port (child) node): > > - reg : address and length of the register set for the port. > > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Mon, Mar 12, 2018 at 01:25:40PM +0800, Chunfeng Yun wrote: > Add two properties of ref_clk and coefficient used by U2 slew rate > calibrate which may vary on different SoCs > > Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> > --- > Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt > index 41e09ed..0d34b2b 100644 > --- a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt > +++ b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt > @@ -27,6 +27,10 @@ Optional properties (controller (parent) node): > - reg : offset and length of register shared by multiple ports, > exclude port's private register. It is needed on mt2701 > and mt8173, but not on mt2712. > + - mediatek,src-ref-clk-mhz : frequency of reference clock for slew rate > + calibrate > + - mediatek,src-coef : coefficient for slew rate calibrate, depends on > + SoC process What are valid values? This is one cell? > > Required properties (port (child) node): > - reg : address and length of the register set for the port. > -- > 1.9.1 > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Sun, 2018-03-18 at 07:48 -0500, Rob Herring wrote: > On Mon, Mar 12, 2018 at 01:25:40PM +0800, Chunfeng Yun wrote: > > Add two properties of ref_clk and coefficient used by U2 slew rate > > calibrate which may vary on different SoCs > > > > Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> > > --- > > Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt | 4 ++++ > > 1 file changed, 4 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt > > index 41e09ed..0d34b2b 100644 > > --- a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt > > +++ b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt > > @@ -27,6 +27,10 @@ Optional properties (controller (parent) node): > > - reg : offset and length of register shared by multiple ports, > > exclude port's private register. It is needed on mt2701 > > and mt8173, but not on mt2712. > > + - mediatek,src-ref-clk-mhz : frequency of reference clock for slew rate > > + calibrate > > + - mediatek,src-coef : coefficient for slew rate calibrate, depends on > > + SoC process > > What are valid values? This is one cell? Yes, one cell, integer type. If need, I'll send a new patch Thanks > > > > > Required properties (port (child) node): > > - reg : address and length of the register set for the port. > > -- > > 1.9.1 > > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt index 41e09ed..0d34b2b 100644 --- a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt +++ b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt @@ -27,6 +27,10 @@ Optional properties (controller (parent) node): - reg : offset and length of register shared by multiple ports, exclude port's private register. It is needed on mt2701 and mt8173, but not on mt2712. + - mediatek,src-ref-clk-mhz : frequency of reference clock for slew rate + calibrate + - mediatek,src-coef : coefficient for slew rate calibrate, depends on + SoC process Required properties (port (child) node): - reg : address and length of the register set for the port.
Add two properties of ref_clk and coefficient used by U2 slew rate calibrate which may vary on different SoCs Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> --- Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt | 4 ++++ 1 file changed, 4 insertions(+)