diff mbox

[U-Boot,v4,2/8] fec_mxc: add support for MX53 processor

Message ID 1294129662-680-2-git-send-email-r64343@freescale.com
State Accepted
Delegated to: Stefano Babic
Headers show

Commit Message

Liu Hui-R64343 Jan. 4, 2011, 8:27 a.m. UTC 
This patch add FEC support for Freescale MX53 processor

Signed-off-by: Jason Liu <r64343@freescale.com>
---
 drivers/net/fec_mxc.c |    2 +-
 drivers/net/fec_mxc.h |    4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

Comments

Stefano Babic Jan. 12, 2011, 9:46 a.m. UTC | #1 
On 01/04/2011 09:27 AM, Jason Liu wrote:
> This patch add FEC support for Freescale MX53 processor
> 
> Signed-off-by: Jason Liu <r64343@freescale.com>
> ---
>  drivers/net/fec_mxc.c |    2 +-
>  drivers/net/fec_mxc.h |    4 ++--
>  2 files changed, 3 insertions(+), 3 deletions(-)
> 
Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic
diff mbox

Patch

diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 0d0f392..652ced4 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -354,7 +354,7 @@  static int fec_open(struct eth_device *edev)
 	 */
 	writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
 		&fec->eth->ecntrl);
-#ifdef CONFIG_MX25
+#if defined(CONFIG_MX25) || defined(CONFIG_MX53)
 	udelay(100);
 	/*
 	 * setup the MII gasket for RMII mode
diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h
index 5d0d69d..1ba5161 100644
--- a/drivers/net/fec_mxc.h
+++ b/drivers/net/fec_mxc.h
@@ -147,7 +147,7 @@  struct ethernet_regs {
 
 	uint32_t res14[7];		/* MBAR_ETH + 0x2E4-2FC */
 
-#ifdef CONFIG_MX25
+#if defined(CONFIG_MX25) || defined(CONFIG_MX53)
 	uint16_t miigsk_cfgr;		/* MBAR_ETH + 0x300 */
 	uint16_t res15[3];		/* MBAR_ETH + 0x302-306 */
 	uint16_t miigsk_enr;		/* MBAR_ETH + 0x308 */
@@ -204,7 +204,7 @@  struct ethernet_regs {
 #define FEC_ECNTRL_RESET		0x00000001	/* reset the FEC */
 #define FEC_ECNTRL_ETHER_EN		0x00000002	/* enable the FEC */
 
-#ifdef CONFIG_MX25
+#if defined(CONFIG_MX25) || defined(CONFIG_MX53)
 /* defines for MIIGSK */
 /* RMII frequency control: 0=50MHz, 1=5MHz */
 #define MIIGSK_CFGR_FRCONT		(1 << 6)