| Message ID | 20180209214015.GA12579@us.ibm.com |
|---|---|
| State | Accepted |
| Headers | show |
| Series | vas: Disable VAS/NX-842 on some P9 revisions | expand |
On Fri, 2018-02-09 at 13:40 -0800, Sukadev Bhattiprolu wrote: > VAS/NX-842 are not functional on some P9 revisions, so disable them > in hardware and skip creating their device tree nodes. > > Since the intent is to prevent OS from configuring VAS/NX, we remove > only the platform device nodes but leave the VAS/NX DT nodes under > xscom (i.e we don't skip add_vas_node() in hdata/spira.c) > > Thanks to input from Michael Ellerman, Michael Neuling. > > Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> > --- > hw/nx.c | 5 +++++ > hw/vas.c | 47 ++++++++++++++++++++++++++++++++++++++++++++--- > include/vas.h | 1 + > 3 files changed, 50 insertions(+), 3 deletions(-) > > diff --git a/hw/nx.c b/hw/nx.c > index 0f6ff04..784a553 100644 > --- a/hw/nx.c > +++ b/hw/nx.c > @@ -24,6 +24,7 @@ > #include <chip.h> > #include <xscom-p9-regs.h> > #include <phys-map.h> > +#include <vas.h> > #include <p9_stop_api.H> > > static void p9_darn_init(void) > @@ -110,6 +111,10 @@ void nx_p9_rng_late_init(void) > static void nx_init_one(struct dt_node *node) > { > nx_create_rng_node(node); > + > + if (vas_nx_disabled()) > + return; > + > nx_create_crypto_node(node); > nx_create_compress_node(node); > } > diff --git a/hw/vas.c b/hw/vas.c > index fb5a1e7..6362f7e 100644 > --- a/hw/vas.c > +++ b/hw/vas.c > @@ -69,6 +69,36 @@ static int vas_scom_write(struct proc_chip *chip, uint64_t > reg, uint64_t val) > return rc; > } > > +/* > + * VAS and hence, NX-842 are disabled in following POWER9 revisions: > + * > + * - Nimbus DD1.X, DD2.01, DD2.1 > + * - Cumulus DD1.0 > + * > + * Return true for those revisions. Return false for others. > + */ > +__attrconst inline bool vas_nx_disabled(void) Minor nit, can you make this vax_nx_enabled() and change the sex throughout the code. A disabled call returning false hurts my head. :-) > +{ > + uint32_t pvr; > + int major, minor; > + struct proc_chip *chip; > + > + chip = next_chip(NULL); > + > + pvr = mfspr(SPR_PVR); > + major = PVR_VERS_MAJ(pvr); > + minor = PVR_VERS_MIN(pvr); > + > + switch (chip->type) { > + case PROC_CHIP_P9_NIMBUS: > + return (major < 2 || (major == 2 && minor <= 1)); > + case PROC_CHIP_P9_CUMULUS: > + return (major == 1 && minor == 0); > + default: > + return false; > + } > +} > + > /* Interface for NX - make sure VAS is fully initialized first */ > __attrconst inline uint64_t vas_get_hvwc_mmio_bar(const int chipid) > { > @@ -110,6 +140,9 @@ static int init_north_ctl(struct proc_chip *chip) > return vas_scom_write(chip, VAS_MISC_N_CTL, val); > } > > +/* > + * Ensure paste instructions are not accepted and MMIO BARs are disabled. > + */ > static inline int reset_north_ctl(struct proc_chip *chip) > { > return vas_scom_write(chip, VAS_MISC_N_CTL, 0ULL); > @@ -399,7 +432,7 @@ static void disable_vas_inst(struct dt_node *np) > /* > * Initialize one VAS instance > */ > -static int init_vas_inst(struct dt_node *np) > +static int init_vas_inst(struct dt_node *np, bool disabled) > { > uint32_t vas_id; > uint64_t xscom_base; > @@ -411,6 +444,11 @@ static int init_vas_inst(struct dt_node *np) > > chip->vas = alloc_vas(chip->id, vas_id, xscom_base); > > + if (disabled) { > + reset_north_ctl(chip); > + return 0; > + } > + > if (alloc_init_wcbs(chip)) > return -1; > > @@ -429,17 +467,20 @@ static int init_vas_inst(struct dt_node *np) > > void vas_init() > { > + bool disabled; > struct dt_node *np; > > if (proc_gen != proc_gen_p9) > return; > > + disabled = vas_nx_disabled(); > + > dt_for_each_compatible(dt_root, np, "ibm,power9-vas-x") { > - if (init_vas_inst(np)) > + if (init_vas_inst(np, disabled)) > goto out; > } > > - vas_initialized = 1; > + vas_initialized = !disabled; > return; > > out: > diff --git a/include/vas.h b/include/vas.h > index 6bc2a1c..2e37908 100644 > --- a/include/vas.h > +++ b/include/vas.h > @@ -37,6 +37,7 @@ > */ > > extern void vas_init(void); > +extern __attrconst bool vas_nx_disabled(void); > extern __attrconst uint64_t vas_get_hvwc_mmio_bar(const int chipid); > extern __attrconst uint64_t vas_get_wcbs_bar(int chipid); >
Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> writes: > diff --git a/hw/vas.c b/hw/vas.c > index fb5a1e7..6362f7e 100644 > --- a/hw/vas.c > +++ b/hw/vas.c > @@ -69,6 +69,36 @@ static int vas_scom_write(struct proc_chip *chip, uint64_t reg, uint64_t val) > return rc; > } > > +/* > + * VAS and hence, NX-842 are disabled in following POWER9 revisions: It's actually paste that is disabled, and we disable VAS/NX so that nothing will use paste. > + * > + * - Nimbus DD1.X, DD2.01, DD2.1 > + * - Cumulus DD1.0 > + * > + * Return true for those revisions. Return false for others. > + */ cheers
Michael Neuling [mikey@neuling.org] wrote: > > + * Return true for those revisions. Return false for others. > > + */ > > +__attrconst inline bool vas_nx_disabled(void) > > Minor nit, can you make this vax_nx_enabled() and change the sex throughout the > code. Sure. Here is the updated patch. --- From 99ecaa18b50e5f43baa39a52336660e6e9a139d0 Mon Sep 17 00:00:00 2001 From: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> Date: Fri, 9 Feb 2018 11:21:30 -0800 Subject: [PATCH 1/1] vas: Disable VAS/NX-842 on some P9 revisions VAS/NX-842 are not functional on some P9 revisions, so disable them in hardware and skip creating their device tree nodes. Since the intent is to prevent OS from configuring VAS/NX, we remove only the platform device nodes but leave the VAS/NX DT nodes under xscom (i.e we don't skip add_vas_node() in hdata/spira.c) Thanks to input from Michael Ellerman, Michael Neuling. Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> --- Changelog[v2] - [Michael Neuling]: Use "_enabled" in the interface name. - [Michael Ellerman, Sukadev]. Update function header comments. --- hw/nx.c | 6 ++++++ hw/vas.c | 55 +++++++++++++++++++++++++++++++++++++++++++++++++++---- include/vas.h | 1 + 3 files changed, 58 insertions(+), 4 deletions(-) diff --git a/hw/nx.c b/hw/nx.c index 0f6ff04..7032c9f 100644 --- a/hw/nx.c +++ b/hw/nx.c @@ -24,6 +24,7 @@ #include <chip.h> #include <xscom-p9-regs.h> #include <phys-map.h> +#include <vas.h> #include <p9_stop_api.H> static void p9_darn_init(void) @@ -110,7 +111,12 @@ void nx_p9_rng_late_init(void) static void nx_init_one(struct dt_node *node) { nx_create_rng_node(node); + + if (!vas_nx_enabled()) + return; + nx_create_crypto_node(node); + nx_create_compress_node(node); } diff --git a/hw/vas.c b/hw/vas.c index fb5a1e7..d8c2b38 100644 --- a/hw/vas.c +++ b/hw/vas.c @@ -69,6 +69,42 @@ static int vas_scom_write(struct proc_chip *chip, uint64_t reg, uint64_t val) return rc; } +/* + * Return true if NX crypto/compression is enabled on this processor. + * + * On POWER8, NX-842 crypto and compression are allowed, but they do not + * use VAS (return true). + * + * On POWER9, NX 842 and GZIP compressions use VAS but the PASTE instruction + * and hence VAS is not enabled in following revisions: + * + * - Nimbus DD1.X, DD2.01, DD2.1 + * - Cumulus DD1.0 + * + * Return false for these revisions. Return true otherwise. + */ +__attrconst inline bool vas_nx_enabled(void) +{ + uint32_t pvr; + int major, minor; + struct proc_chip *chip; + + chip = next_chip(NULL); + + pvr = mfspr(SPR_PVR); + major = PVR_VERS_MAJ(pvr); + minor = PVR_VERS_MIN(pvr); + + switch (chip->type) { + case PROC_CHIP_P9_NIMBUS: + return (major > 2 || (major == 2 && minor > 1)); + case PROC_CHIP_P9_CUMULUS: + return (major > 1 || minor > 0); + default: + return true; + } +} + /* Interface for NX - make sure VAS is fully initialized first */ __attrconst inline uint64_t vas_get_hvwc_mmio_bar(const int chipid) { @@ -110,6 +146,9 @@ static int init_north_ctl(struct proc_chip *chip) return vas_scom_write(chip, VAS_MISC_N_CTL, val); } +/* + * Ensure paste instructions are not accepted and MMIO BARs are disabled. + */ static inline int reset_north_ctl(struct proc_chip *chip) { return vas_scom_write(chip, VAS_MISC_N_CTL, 0ULL); @@ -397,9 +436,9 @@ static void disable_vas_inst(struct dt_node *np) } /* - * Initialize one VAS instance + * Initialize one VAS instance and enable it if @enable is true. */ -static int init_vas_inst(struct dt_node *np) +static int init_vas_inst(struct dt_node *np, bool enable) { uint32_t vas_id; uint64_t xscom_base; @@ -411,6 +450,11 @@ static int init_vas_inst(struct dt_node *np) chip->vas = alloc_vas(chip->id, vas_id, xscom_base); + if (!enable) { + reset_north_ctl(chip); + return 0; + } + if (alloc_init_wcbs(chip)) return -1; @@ -429,17 +473,20 @@ static int init_vas_inst(struct dt_node *np) void vas_init() { + bool enabled; struct dt_node *np; if (proc_gen != proc_gen_p9) return; + enabled = vas_nx_enabled(); + dt_for_each_compatible(dt_root, np, "ibm,power9-vas-x") { - if (init_vas_inst(np)) + if (init_vas_inst(np, enabled)) goto out; } - vas_initialized = 1; + vas_initialized = enabled; return; out: diff --git a/include/vas.h b/include/vas.h index 6bc2a1c..f8c7add 100644 --- a/include/vas.h +++ b/include/vas.h @@ -37,6 +37,7 @@ */ extern void vas_init(void); +extern __attrconst bool vas_nx_enabled(void); extern __attrconst uint64_t vas_get_hvwc_mmio_bar(const int chipid); extern __attrconst uint64_t vas_get_wcbs_bar(int chipid);
Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> writes: > Michael Neuling [mikey@neuling.org] wrote: >> > + * Return true for those revisions. Return false for others. >> > + */ >> > +__attrconst inline bool vas_nx_disabled(void) >> >> Minor nit, can you make this vax_nx_enabled() and change the sex throughout the >> code. > > Sure. Here is the updated patch. > > --- > From 99ecaa18b50e5f43baa39a52336660e6e9a139d0 Mon Sep 17 00:00:00 2001 > From: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> > Date: Fri, 9 Feb 2018 11:21:30 -0800 > Subject: [PATCH 1/1] vas: Disable VAS/NX-842 on some P9 revisions > > VAS/NX-842 are not functional on some P9 revisions, so disable them > in hardware and skip creating their device tree nodes. > > Since the intent is to prevent OS from configuring VAS/NX, we remove > only the platform device nodes but leave the VAS/NX DT nodes under > xscom (i.e we don't skip add_vas_node() in hdata/spira.c) > > Thanks to input from Michael Ellerman, Michael Neuling. > > Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> > --- This looks good to me. I defer to Stewart for coding style etc. Reviewed-by: Michael Ellerman <mpe@ellerman.id.au> cheers > Changelog[v2] > - [Michael Neuling]: Use "_enabled" in the interface name. > - [Michael Ellerman, Sukadev]. Update function header comments. > --- > hw/nx.c | 6 ++++++ > hw/vas.c | 55 +++++++++++++++++++++++++++++++++++++++++++++++++++---- > include/vas.h | 1 + > 3 files changed, 58 insertions(+), 4 deletions(-) > > diff --git a/hw/nx.c b/hw/nx.c > index 0f6ff04..7032c9f 100644 > --- a/hw/nx.c > +++ b/hw/nx.c > @@ -24,6 +24,7 @@ > #include <chip.h> > #include <xscom-p9-regs.h> > #include <phys-map.h> > +#include <vas.h> > #include <p9_stop_api.H> > > static void p9_darn_init(void) > @@ -110,7 +111,12 @@ void nx_p9_rng_late_init(void) > static void nx_init_one(struct dt_node *node) > { > nx_create_rng_node(node); > + > + if (!vas_nx_enabled()) > + return; > + > nx_create_crypto_node(node); > + > nx_create_compress_node(node); > } > > diff --git a/hw/vas.c b/hw/vas.c > index fb5a1e7..d8c2b38 100644 > --- a/hw/vas.c > +++ b/hw/vas.c > @@ -69,6 +69,42 @@ static int vas_scom_write(struct proc_chip *chip, uint64_t reg, uint64_t val) > return rc; > } > > +/* > + * Return true if NX crypto/compression is enabled on this processor. > + * > + * On POWER8, NX-842 crypto and compression are allowed, but they do not > + * use VAS (return true). > + * > + * On POWER9, NX 842 and GZIP compressions use VAS but the PASTE instruction > + * and hence VAS is not enabled in following revisions: > + * > + * - Nimbus DD1.X, DD2.01, DD2.1 > + * - Cumulus DD1.0 > + * > + * Return false for these revisions. Return true otherwise. > + */ > +__attrconst inline bool vas_nx_enabled(void) > +{ > + uint32_t pvr; > + int major, minor; > + struct proc_chip *chip; > + > + chip = next_chip(NULL); > + > + pvr = mfspr(SPR_PVR); > + major = PVR_VERS_MAJ(pvr); > + minor = PVR_VERS_MIN(pvr); > + > + switch (chip->type) { > + case PROC_CHIP_P9_NIMBUS: > + return (major > 2 || (major == 2 && minor > 1)); > + case PROC_CHIP_P9_CUMULUS: > + return (major > 1 || minor > 0); > + default: > + return true; > + } > +} > + > /* Interface for NX - make sure VAS is fully initialized first */ > __attrconst inline uint64_t vas_get_hvwc_mmio_bar(const int chipid) > { > @@ -110,6 +146,9 @@ static int init_north_ctl(struct proc_chip *chip) > return vas_scom_write(chip, VAS_MISC_N_CTL, val); > } > > +/* > + * Ensure paste instructions are not accepted and MMIO BARs are disabled. > + */ > static inline int reset_north_ctl(struct proc_chip *chip) > { > return vas_scom_write(chip, VAS_MISC_N_CTL, 0ULL); > @@ -397,9 +436,9 @@ static void disable_vas_inst(struct dt_node *np) > } > > /* > - * Initialize one VAS instance > + * Initialize one VAS instance and enable it if @enable is true. > */ > -static int init_vas_inst(struct dt_node *np) > +static int init_vas_inst(struct dt_node *np, bool enable) > { > uint32_t vas_id; > uint64_t xscom_base; > @@ -411,6 +450,11 @@ static int init_vas_inst(struct dt_node *np) > > chip->vas = alloc_vas(chip->id, vas_id, xscom_base); > > + if (!enable) { > + reset_north_ctl(chip); > + return 0; > + } > + > if (alloc_init_wcbs(chip)) > return -1; > > @@ -429,17 +473,20 @@ static int init_vas_inst(struct dt_node *np) > > void vas_init() > { > + bool enabled; > struct dt_node *np; > > if (proc_gen != proc_gen_p9) > return; > > + enabled = vas_nx_enabled(); > + > dt_for_each_compatible(dt_root, np, "ibm,power9-vas-x") { > - if (init_vas_inst(np)) > + if (init_vas_inst(np, enabled)) > goto out; > } > > - vas_initialized = 1; > + vas_initialized = enabled; > return; > > out: > diff --git a/include/vas.h b/include/vas.h > index 6bc2a1c..f8c7add 100644 > --- a/include/vas.h > +++ b/include/vas.h > @@ -37,6 +37,7 @@ > */ > > extern void vas_init(void); > +extern __attrconst bool vas_nx_enabled(void); > extern __attrconst uint64_t vas_get_hvwc_mmio_bar(const int chipid); > extern __attrconst uint64_t vas_get_wcbs_bar(int chipid); > > -- > 2.7.4
Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> writes: > Michael Neuling [mikey@neuling.org] wrote: >> > + * Return true for those revisions. Return false for others. >> > + */ >> > +__attrconst inline bool vas_nx_disabled(void) >> >> Minor nit, can you make this vax_nx_enabled() and change the sex throughout the >> code. > > Sure. Here is the updated patch. > > --- > From 99ecaa18b50e5f43baa39a52336660e6e9a139d0 Mon Sep 17 00:00:00 2001 > From: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> > Date: Fri, 9 Feb 2018 11:21:30 -0800 > Subject: [PATCH 1/1] vas: Disable VAS/NX-842 on some P9 revisions > > VAS/NX-842 are not functional on some P9 revisions, so disable them > in hardware and skip creating their device tree nodes. > > Since the intent is to prevent OS from configuring VAS/NX, we remove > only the platform device nodes but leave the VAS/NX DT nodes under > xscom (i.e we don't skip add_vas_node() in hdata/spira.c) > > Thanks to input from Michael Ellerman, Michael Neuling. > > Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> > --- > > Changelog[v2] > - [Michael Neuling]: Use "_enabled" in the interface name. > - [Michael Ellerman, Sukadev]. Update function header comments. > --- > hw/nx.c | 6 ++++++ > hw/vas.c | 55 +++++++++++++++++++++++++++++++++++++++++++++++++++---- > include/vas.h | 1 + > 3 files changed, 58 insertions(+), 4 deletions(-) Thanks for this, merged to master as of 31e5e988632f6554f70ed3e4072aef4245ee7b73 and is present in v5.10-rc3
On Thu, Feb 15, 2018 at 5:48 PM, Stewart Smith <stewart@linux.vnet.ibm.com> wrote: > Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> writes: >> Michael Neuling [mikey@neuling.org] wrote: >>> > + * Return true for those revisions. Return false for others. >>> > + */ >>> > +__attrconst inline bool vas_nx_disabled(void) >>> >>> Minor nit, can you make this vax_nx_enabled() and change the sex throughout the >>> code. >> >> Sure. Here is the updated patch. >> >> --- >> From 99ecaa18b50e5f43baa39a52336660e6e9a139d0 Mon Sep 17 00:00:00 2001 >> From: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> >> Date: Fri, 9 Feb 2018 11:21:30 -0800 >> Subject: [PATCH 1/1] vas: Disable VAS/NX-842 on some P9 revisions >> >> VAS/NX-842 are not functional on some P9 revisions, so disable them >> in hardware and skip creating their device tree nodes. >> >> Since the intent is to prevent OS from configuring VAS/NX, we remove >> only the platform device nodes but leave the VAS/NX DT nodes under >> xscom (i.e we don't skip add_vas_node() in hdata/spira.c) >> >> Thanks to input from Michael Ellerman, Michael Neuling. >> >> Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> >> --- >> >> Changelog[v2] >> - [Michael Neuling]: Use "_enabled" in the interface name. >> - [Michael Ellerman, Sukadev]. Update function header comments. >> --- >> hw/nx.c | 6 ++++++ >> hw/vas.c | 55 +++++++++++++++++++++++++++++++++++++++++++++++++++---- >> include/vas.h | 1 + >> 3 files changed, 58 insertions(+), 4 deletions(-) > > Thanks for this, merged to master as of > 31e5e988632f6554f70ed3e4072aef4245ee7b73 and is present in v5.10-rc3 We probably want to backport this to 5.9.x too > > > -- > Stewart Smith > OPAL Architect, IBM. > > _______________________________________________ > Skiboot mailing list > Skiboot@lists.ozlabs.org > https://lists.ozlabs.org/listinfo/skiboot
diff --git a/hw/nx.c b/hw/nx.c index 0f6ff04..784a553 100644 --- a/hw/nx.c +++ b/hw/nx.c @@ -24,6 +24,7 @@ #include <chip.h> #include <xscom-p9-regs.h> #include <phys-map.h> +#include <vas.h> #include <p9_stop_api.H> static void p9_darn_init(void) @@ -110,6 +111,10 @@ void nx_p9_rng_late_init(void) static void nx_init_one(struct dt_node *node) { nx_create_rng_node(node); + + if (vas_nx_disabled()) + return; + nx_create_crypto_node(node); nx_create_compress_node(node); } diff --git a/hw/vas.c b/hw/vas.c index fb5a1e7..6362f7e 100644 --- a/hw/vas.c +++ b/hw/vas.c @@ -69,6 +69,36 @@ static int vas_scom_write(struct proc_chip *chip, uint64_t reg, uint64_t val) return rc; } +/* + * VAS and hence, NX-842 are disabled in following POWER9 revisions: + * + * - Nimbus DD1.X, DD2.01, DD2.1 + * - Cumulus DD1.0 + * + * Return true for those revisions. Return false for others. + */ +__attrconst inline bool vas_nx_disabled(void) +{ + uint32_t pvr; + int major, minor; + struct proc_chip *chip; + + chip = next_chip(NULL); + + pvr = mfspr(SPR_PVR); + major = PVR_VERS_MAJ(pvr); + minor = PVR_VERS_MIN(pvr); + + switch (chip->type) { + case PROC_CHIP_P9_NIMBUS: + return (major < 2 || (major == 2 && minor <= 1)); + case PROC_CHIP_P9_CUMULUS: + return (major == 1 && minor == 0); + default: + return false; + } +} + /* Interface for NX - make sure VAS is fully initialized first */ __attrconst inline uint64_t vas_get_hvwc_mmio_bar(const int chipid) { @@ -110,6 +140,9 @@ static int init_north_ctl(struct proc_chip *chip) return vas_scom_write(chip, VAS_MISC_N_CTL, val); } +/* + * Ensure paste instructions are not accepted and MMIO BARs are disabled. + */ static inline int reset_north_ctl(struct proc_chip *chip) { return vas_scom_write(chip, VAS_MISC_N_CTL, 0ULL); @@ -399,7 +432,7 @@ static void disable_vas_inst(struct dt_node *np) /* * Initialize one VAS instance */ -static int init_vas_inst(struct dt_node *np) +static int init_vas_inst(struct dt_node *np, bool disabled) { uint32_t vas_id; uint64_t xscom_base; @@ -411,6 +444,11 @@ static int init_vas_inst(struct dt_node *np) chip->vas = alloc_vas(chip->id, vas_id, xscom_base); + if (disabled) { + reset_north_ctl(chip); + return 0; + } + if (alloc_init_wcbs(chip)) return -1; @@ -429,17 +467,20 @@ static int init_vas_inst(struct dt_node *np) void vas_init() { + bool disabled; struct dt_node *np; if (proc_gen != proc_gen_p9) return; + disabled = vas_nx_disabled(); + dt_for_each_compatible(dt_root, np, "ibm,power9-vas-x") { - if (init_vas_inst(np)) + if (init_vas_inst(np, disabled)) goto out; } - vas_initialized = 1; + vas_initialized = !disabled; return; out: diff --git a/include/vas.h b/include/vas.h index 6bc2a1c..2e37908 100644 --- a/include/vas.h +++ b/include/vas.h @@ -37,6 +37,7 @@ */ extern void vas_init(void); +extern __attrconst bool vas_nx_disabled(void); extern __attrconst uint64_t vas_get_hvwc_mmio_bar(const int chipid); extern __attrconst uint64_t vas_get_wcbs_bar(int chipid);
VAS/NX-842 are not functional on some P9 revisions, so disable them in hardware and skip creating their device tree nodes. Since the intent is to prevent OS from configuring VAS/NX, we remove only the platform device nodes but leave the VAS/NX DT nodes under xscom (i.e we don't skip add_vas_node() in hdata/spira.c) Thanks to input from Michael Ellerman, Michael Neuling. Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> --- hw/nx.c | 5 +++++ hw/vas.c | 47 ++++++++++++++++++++++++++++++++++++++++++++--- include/vas.h | 1 + 3 files changed, 50 insertions(+), 3 deletions(-)