| Message ID | 1294245562-8261-1-git-send-email-galak@kernel.crashing.org |
|---|---|
| State | Accepted |
| Commit | 45a68135c12bf7d534f3ce25bef493e16d32cedb |
| Delegated to: | Kumar Gala |
| Headers | show |
On Jan 5, 2011, at 10:39 AM, Kumar Gala wrote: > We set the L1 dache register with a bogus register value. Need to be > using 'r3' instead of 'r0'. > > Reported-by: John Traill <john.traill@freescale.com> > Signed-off-by: Kumar Gala <galak@kernel.crashing.org> > --- > arch/powerpc/cpu/mpc85xx/start.S | 4 ++-- > 1 files changed, 2 insertions(+), 2 deletions(-) applied to 85xx - k
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 945c1b8..fa98af6 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -1,5 +1,5 @@ /* - * Copyright 2004, 2007-2010 Freescale Semiconductor, Inc. + * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc. * Copyright (C) 2003 Motorola,Inc. * * See file CREDITS for list of people who contributed to this @@ -753,7 +753,7 @@ dcache_disable: lis r4,0 ori r4,r4,L1CSR0_DCE andc r3,r3,r4 - mtspr L1CSR0,r0 + mtspr L1CSR0,r3 isync blr
We set the L1 dache register with a bogus register value. Need to be using 'r3' instead of 'r0'. Reported-by: John Traill <john.traill@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> --- arch/powerpc/cpu/mpc85xx/start.S | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-)