diff mbox series

[10/26] KVM: PPC: Book3S PR: set MSR HV bit accordingly for PPC970 and others.

Message ID 1515665499-31710-11-git-send-email-wei.guo.simon@gmail.com
State Changes Requested
Headers show
Series [01/26] KVM: PPC: Book3S PR: Move kvmppc_save_tm/kvmppc_restore_tm to separate file | expand

Commit Message

Simon Guo Jan. 11, 2018, 10:11 a.m. UTC 
From: Simon Guo <wei.guo.simon@gmail.com>

Apple G5 machines(PPC970/FX/GX/MP) have supervisor mode disabled and
MSR HV bit is forced into 1. We should follow this in PR KVM guest.

This patch set MSR HV=1 for G5 machines and HV=0 for others on PR
KVM guest.

Signed-off-by: Simon Guo <wei.guo.simon@gmail.com>
Suggested-by: Paul Mackerras <paulus@ozlabs.org>
---
 arch/powerpc/kvm/book3s_pr.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

Comments

Paul Mackerras Jan. 23, 2018, 5:51 a.m. UTC | #1 
On Thu, Jan 11, 2018 at 06:11:23PM +0800, wei.guo.simon@gmail.com wrote:
> From: Simon Guo <wei.guo.simon@gmail.com>
> 
> Apple G5 machines(PPC970/FX/GX/MP) have supervisor mode disabled and
> MSR HV bit is forced into 1. We should follow this in PR KVM guest.
> 
> This patch set MSR HV=1 for G5 machines and HV=0 for others on PR
> KVM guest.
> 
> Signed-off-by: Simon Guo <wei.guo.simon@gmail.com>
> Suggested-by: Paul Mackerras <paulus@ozlabs.org>

Reviewed-by: Paul Mackerras <paulus@ozlabs.org>
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diff mbox series

Patch

diff --git a/arch/powerpc/kvm/book3s_pr.c b/arch/powerpc/kvm/book3s_pr.c
index 7ec866a..b2f7566 100644
--- a/arch/powerpc/kvm/book3s_pr.c
+++ b/arch/powerpc/kvm/book3s_pr.c
@@ -320,6 +320,7 @@  static void kvmppc_recalc_shadow_msr(struct kvm_vcpu *vcpu)
 {
 	ulong guest_msr = kvmppc_get_msr(vcpu);
 	ulong smsr = guest_msr;
+	u32 guest_pvr = vcpu->arch.pvr;
 
 	/* Guest MSR values */
 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
@@ -334,7 +335,16 @@  static void kvmppc_recalc_shadow_msr(struct kvm_vcpu *vcpu)
 	smsr |= (guest_msr & vcpu->arch.guest_owned_ext);
 	/* 64-bit Process MSR values */
 #ifdef CONFIG_PPC_BOOK3S_64
-	smsr |= MSR_ISF | MSR_HV;
+	smsr |= MSR_ISF;
+
+	/* for PPC970 chip, its HV bit is hard-wired to 1. For others,
+	 * we should clear HV bit.
+	 */
+	if ((PVR_VER(guest_pvr) == PVR_970) ||
+	    (PVR_VER(guest_pvr) == PVR_970FX) ||
+	    (PVR_VER(guest_pvr) == PVR_970MP) ||
+	    (PVR_VER(guest_pvr) == PVR_970GX))
+		smsr |= MSR_HV;
 #endif
 	vcpu->arch.shadow_msr = smsr;
 }