| Message ID | 20171010101828.5950-1-npiggin@gmail.com |
|---|---|
| State | Accepted |
| Headers | show |
| Series | KVM: PPC: Book3S HV: POWER9 more doorbell fixes | expand |
On Tue, 10 Oct 2017 20:18:28 +1000 Nicholas Piggin <npiggin@gmail.com> wrote: > - Add another case where msgsync is required. > - Required barrier sequence for global doorbells is msgsync ; lwsync > - POWER9 DD1 has a different barrier sequence that we don't implement, > so remove This last item was not included in the patch, it slipped past. I think the changelog can just be changed to remove it. Fixing up DD1 should be a different patch if we want to bother with it. Guess either we add the darn sequence for msgsync, or add support for xive IPIs? Thanks, Nick -- To unsubscribe from this list: send the line "unsubscribe kvm-ppc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Tue, Oct 10, 2017 at 08:18:28PM +1000, Nicholas Piggin wrote: > - Add another case where msgsync is required. > - Required barrier sequence for global doorbells is msgsync ; lwsync > - POWER9 DD1 has a different barrier sequence that we don't implement, > so remove > > When msgsnd is used for IPIs to other cores, msgsync must be executed by > the target to order stores performed on the source before its msgsnd > (provided the source executes the appropriate sync). > > Fixes: 1704a81ccebc ("KVM: PPC: Book3S HV: Use msgsnd for IPIs to other cores on POWER9") > Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Thanks, applied to my kvm-ppc-fixes branch (minus the comment about DD1). Paul. -- To unsubscribe from this list: send the line "unsubscribe kvm-ppc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S b/arch/powerpc/kvm/book3s_hv_rmhandlers.S index 663a4a861e7f..90c07421eba2 100644 --- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S +++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S @@ -1300,6 +1300,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) bne 3f BEGIN_FTR_SECTION PPC_MSGSYNC + lwsync END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300) lbz r0, HSTATE_HOST_IPI(r13) cmpwi r0, 0 @@ -2761,6 +2762,10 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) PPC_MSGCLR(6) /* see if it's a host IPI */ li r3, 1 +BEGIN_FTR_SECTION + PPC_MSGSYNC + lwsync +END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300) lbz r0, HSTATE_HOST_IPI(r13) cmpwi r0, 0 bnelr
- Add another case where msgsync is required. - Required barrier sequence for global doorbells is msgsync ; lwsync - POWER9 DD1 has a different barrier sequence that we don't implement, so remove When msgsnd is used for IPIs to other cores, msgsync must be executed by the target to order stores performed on the source before its msgsnd (provided the source executes the appropriate sync). Fixes: 1704a81ccebc ("KVM: PPC: Book3S HV: Use msgsnd for IPIs to other cores on POWER9") Signed-off-by: Nicholas Piggin <npiggin@gmail.com> --- arch/powerpc/kvm/book3s_hv_rmhandlers.S | 5 +++++ 1 file changed, 5 insertions(+)