Fix ICEs with ss{e,e2,se3} builtins with -mno-mmx (PR target/82483)

Hi!

The following builtins have {SSE,SSE2,SSSE3} CPUID, yet they have
MMX register operands (either input or output or both).
As -mno-mmx doesn't imply -mno-sse, we get ICEs on these though, because
with MMX disabled it is not possible to emit them.

The following patch cheats and declares these builtins to require
both the MMX and {SSE,SSE2,SSSE3} ISA, making them unavailable in -mno-mmx
code, but I think it is the right thing to do, when somebody uses -mno-mmx,
the intent is usually not to have any instructions touching the MMX register
file and thus needing EMMS etc.

Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?

2017-10-09  Jakub Jelinek  <jakub@redhat.com>

	PR target/82483
	* config/i386/i386.c (ix86_init_mmx_sse_builtins): Add
	OPTION_MASK_ISA_MMX for __builtin_ia32_maskmovq,
	__builtin_ia32_vec_ext_v4hi and __builtin_ia32_vec_set_v4hi.
	(ix86_expand_builtin): Treat OPTION_MASK_ISA_MMX similarly
	to OPTION_MASK_ISA_AVX512VL - builtins that have both
	OPTION_MASK_ISA_MMX and some other bit set require both
	mmx and the ISAs without the mmx bit.
	* config/i386/i386-builtin.def (__builtin_ia32_cvtps2pi,
	__builtin_ia32_cvttps2pi, __builtin_ia32_cvtpi2ps,
	__builtin_ia32_pavgb, __builtin_ia32_pavgw, __builtin_ia32_pmulhuw,
	__builtin_ia32_pmaxub, __builtin_ia32_pmaxsw, __builtin_ia32_pminub,
	__builtin_ia32_pminsw, __builtin_ia32_psadbw, __builtin_ia32_pmovmskb,
	__builtin_ia32_pshufw, __builtin_ia32_cvtpd2pi,
	__builtin_ia32_cvttpd2pi, __builtin_ia32_cvtpi2pd,
	__builtin_ia32_pmuludq, __builtin_ia32_pabsb, __builtin_ia32_pabsw,
	__builtin_ia32_pabsd, __builtin_ia32_phaddw, __builtin_ia32_phaddd,
	__builtin_ia32_phaddsw, __builtin_ia32_phsubw, __builtin_ia32_phsubd,
	__builtin_ia32_phsubsw, __builtin_ia32_pmaddubsw,
	__builtin_ia32_pmulhrsw, __builtin_ia32_pshufb, __builtin_ia32_psignb,
	__builtin_ia32_psignw, __builtin_ia32_psignd): Add OPTION_MASK_ISA_MMX.

	* gcc.target/i386/pr82483.c: New test.


	Jakub

On Mon, Oct 9, 2017 at 9:16 PM, Jakub Jelinek <jakub@redhat.com> wrote:
> Hi!
>
> The following builtins have {SSE,SSE2,SSSE3} CPUID, yet they have
> MMX register operands (either input or output or both).
> As -mno-mmx doesn't imply -mno-sse, we get ICEs on these though, because
> with MMX disabled it is not possible to emit them.
>
> The following patch cheats and declares these builtins to require
> both the MMX and {SSE,SSE2,SSSE3} ISA, making them unavailable in -mno-mmx
> code, but I think it is the right thing to do, when somebody uses -mno-mmx,
> the intent is usually not to have any instructions touching the MMX register
> file and thus needing EMMS etc.
>
> Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?

Hm, I remember there was similar patch for PR79565 [1], which seems
related. Does your patch also fix all builtins that HJ's patch touch?

[1] https://gcc.gnu.org/ml/gcc-patches/2017-08/msg00751.html

Uros.

> 2017-10-09  Jakub Jelinek  <jakub@redhat.com>
>
>         PR target/82483
>         * config/i386/i386.c (ix86_init_mmx_sse_builtins): Add
>         OPTION_MASK_ISA_MMX for __builtin_ia32_maskmovq,
>         __builtin_ia32_vec_ext_v4hi and __builtin_ia32_vec_set_v4hi.
>         (ix86_expand_builtin): Treat OPTION_MASK_ISA_MMX similarly
>         to OPTION_MASK_ISA_AVX512VL - builtins that have both
>         OPTION_MASK_ISA_MMX and some other bit set require both
>         mmx and the ISAs without the mmx bit.
>         * config/i386/i386-builtin.def (__builtin_ia32_cvtps2pi,
>         __builtin_ia32_cvttps2pi, __builtin_ia32_cvtpi2ps,
>         __builtin_ia32_pavgb, __builtin_ia32_pavgw, __builtin_ia32_pmulhuw,
>         __builtin_ia32_pmaxub, __builtin_ia32_pmaxsw, __builtin_ia32_pminub,
>         __builtin_ia32_pminsw, __builtin_ia32_psadbw, __builtin_ia32_pmovmskb,
>         __builtin_ia32_pshufw, __builtin_ia32_cvtpd2pi,
>         __builtin_ia32_cvttpd2pi, __builtin_ia32_cvtpi2pd,
>         __builtin_ia32_pmuludq, __builtin_ia32_pabsb, __builtin_ia32_pabsw,
>         __builtin_ia32_pabsd, __builtin_ia32_phaddw, __builtin_ia32_phaddd,
>         __builtin_ia32_phaddsw, __builtin_ia32_phsubw, __builtin_ia32_phsubd,
>         __builtin_ia32_phsubsw, __builtin_ia32_pmaddubsw,
>         __builtin_ia32_pmulhrsw, __builtin_ia32_pshufb, __builtin_ia32_psignb,
>         __builtin_ia32_psignw, __builtin_ia32_psignd): Add OPTION_MASK_ISA_MMX.
>
>         * gcc.target/i386/pr82483.c: New test.
>
> --- gcc/config/i386/i386.c.jj   2017-10-09 09:41:21.000000000 +0200
> +++ gcc/config/i386/i386.c      2017-10-09 10:54:05.763679093 +0200
> @@ -32988,7 +32988,9 @@ ix86_init_mmx_sse_builtins (void)
>                     UNSIGNED_FTYPE_VOID, IX86_BUILTIN_STMXCSR);
>
>    /* SSE or 3DNow!A */
> -  def_builtin (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A,
> +  def_builtin (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A
> +              /* As it uses V4HImode, we have to require -mmmx too.  */
> +              | OPTION_MASK_ISA_MMX,
>                "__builtin_ia32_maskmovq", VOID_FTYPE_V8QI_V8QI_PCHAR,
>                IX86_BUILTIN_MASKMOVQ);
>
> @@ -33426,7 +33428,9 @@ ix86_init_mmx_sse_builtins (void)
>    def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v8hi",
>                      HI_FTYPE_V8HI_INT, IX86_BUILTIN_VEC_EXT_V8HI);
>
> -  def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A,
> +  def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A
> +                    /* As it uses V4HImode, we have to require -mmmx too.  */
> +                    | OPTION_MASK_ISA_MMX,
>                      "__builtin_ia32_vec_ext_v4hi",
>                      HI_FTYPE_V4HI_INT, IX86_BUILTIN_VEC_EXT_V4HI);
>
> @@ -33450,7 +33454,9 @@ ix86_init_mmx_sse_builtins (void)
>    def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_set_v8hi",
>                      V8HI_FTYPE_V8HI_HI_INT, IX86_BUILTIN_VEC_SET_V8HI);
>
> -  def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A,
> +  def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A
> +                    /* As it uses V4HImode, we have to require -mmmx too.  */
> +                    | OPTION_MASK_ISA_MMX,
>                      "__builtin_ia32_vec_set_v4hi",
>                      V4HI_FTYPE_V4HI_HI_INT, IX86_BUILTIN_VEC_SET_V4HI);
>
> @@ -37914,18 +37920,23 @@ ix86_expand_builtin (tree exp, rtx targe
>       Originally the builtin was not created if it wasn't applicable to the
>       current ISA based on the command line switches.  With function specific
>       options, we need to check in the context of the function making the call
> -     whether it is supported.  Treat AVX512VL specially.  For other flags,
> +     whether it is supported.  Treat AVX512VL and MMX specially.  For other flags,
>       if isa includes more than one ISA bit, treat those are requiring any
>       of them.  For AVX512VL, require both AVX512VL and the non-AVX512VL
> -     ISAs.  Similarly for 64BIT, but we shouldn't be building such builtins
> +     ISAs.  Likewise for MMX, require both MMX and the non-MMX ISAs.
> +     Similarly for 64BIT, but we shouldn't be building such builtins
>       at all, -m64 is a whole TU option.  */
>    if (((ix86_builtins_isa[fcode].isa
> -       & ~(OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_64BIT))
> +       & ~(OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_MMX
> +           | OPTION_MASK_ISA_64BIT))
>         && !(ix86_builtins_isa[fcode].isa
> -           & ~(OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_64BIT)
> +           & ~(OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_MMX
> +               | OPTION_MASK_ISA_64BIT)
>             & ix86_isa_flags))
>        || ((ix86_builtins_isa[fcode].isa & OPTION_MASK_ISA_AVX512VL)
>           && !(ix86_isa_flags & OPTION_MASK_ISA_AVX512VL))
> +      || ((ix86_builtins_isa[fcode].isa & OPTION_MASK_ISA_MMX)
> +         && !(ix86_isa_flags & OPTION_MASK_ISA_MMX))
>        || (ix86_builtins_isa[fcode].isa2
>           && !(ix86_builtins_isa[fcode].isa2 & ix86_isa_flags2)))
>      {
> --- gcc/config/i386/i386-builtin.def.jj 2017-09-01 09:26:50.000000000 +0200
> +++ gcc/config/i386/i386-builtin.def    2017-10-09 11:04:20.486875768 +0200
> @@ -505,10 +505,10 @@ BDESC (OPTION_MASK_ISA_SSE, CODE_FOR_sqr
>  BDESC (OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF)
>  BDESC (OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF)
>  BDESC (OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF)
> -BDESC (OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF)
> +BDESC (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF)
>  BDESC (OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF)
>  BDESC (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF)
> -BDESC (OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF)
> +BDESC (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF)
>  BDESC (OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF)
>  BDESC (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF)
>
> @@ -562,7 +562,7 @@ BDESC (OPTION_MASK_ISA_SSE, CODE_FOR_sse
>  BDESC (OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_highv4sf, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF)
>  BDESC (OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_lowv4sf, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF)
>
> -BDESC (OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI)
> +BDESC (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI)
>  BDESC (OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI)
>  BDESC (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI)
>
> @@ -576,19 +576,19 @@ BDESC (OPTION_MASK_ISA_SSE, CODE_FOR_abs
>  BDESC (OPTION_MASK_ISA_SSE, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128)
>
>  /* SSE MMX or 3Dnow!A */
> -BDESC (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)
> -BDESC (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
> -BDESC (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
> -
> -BDESC (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)
> -BDESC (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
> -BDESC (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)
> -BDESC (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
> +BDESC (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A | OPTION_MASK_ISA_MMX, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)
> +BDESC (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A | OPTION_MASK_ISA_MMX, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
> +BDESC (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A | OPTION_MASK_ISA_MMX, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
> +
> +BDESC (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A | OPTION_MASK_ISA_MMX, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)
> +BDESC (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A | OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
> +BDESC (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A | OPTION_MASK_ISA_MMX, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)
> +BDESC (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A | OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
>
> -BDESC (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI)
> -BDESC (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI)
> +BDESC (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A | OPTION_MASK_ISA_MMX, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI)
> +BDESC (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A | OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI)
>
> -BDESC (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT)
> +BDESC (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A | OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT)
>
>  /* SSE2 */
>  BDESC (OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT)
> @@ -600,12 +600,12 @@ BDESC (OPTION_MASK_ISA_SSE2, CODE_FOR_ss
>  BDESC (OPTION_MASK_ISA_SSE2, CODE_FOR_floatv4siv4sf2, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI)
>
>  BDESC (OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF)
> -BDESC (OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF)
> +BDESC (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_MMX, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF)
>  BDESC (OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF)
>  BDESC (OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF)
> -BDESC (OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF)
> +BDESC (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_MMX, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF)
>
> -BDESC (OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI)
> +BDESC (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_MMX, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI)
>
>  BDESC (OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF)
>  BDESC (OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF)
> @@ -721,7 +721,7 @@ BDESC (OPTION_MASK_ISA_SSE2, CODE_FOR_ss
>  BDESC (OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI)
>  BDESC (OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI)
>
> -BDESC (OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI)
> +BDESC (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_MMX, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI)
>  BDESC (OPTION_MASK_ISA_SSE2, CODE_FOR_vec_widen_umult_even_v4si, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI)
>
>  BDESC (OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI)
> @@ -777,36 +777,36 @@ BDESC (OPTION_MASK_ISA_SSE3, CODE_FOR_ss
>
>  /* SSSE3 */
>  BDESC (OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI)
> -BDESC (OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI)
> +BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI)
>  BDESC (OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI)
> -BDESC (OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI)
> +BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI)
>  BDESC (OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI)
> -BDESC (OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI)
> +BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI)
>
>  BDESC (OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI)
> -BDESC (OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
> +BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
>  BDESC (OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI)
> -BDESC (OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)
> +BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)
>  BDESC (OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI)
> -BDESC (OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
> +BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
>  BDESC (OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI)
> -BDESC (OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
> +BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
>  BDESC (OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI)
> -BDESC (OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)
> +BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)
>  BDESC (OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI)
> -BDESC (OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
> +BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
>  BDESC (OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI)
> -BDESC (OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI)
> +BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI)
>  BDESC (OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI)
> -BDESC (OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
> +BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
>  BDESC (OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI)
> -BDESC (OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)
> +BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)
>  BDESC (OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI)
> -BDESC (OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)
> +BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)
>  BDESC (OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI)
> -BDESC (OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
> +BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
>  BDESC (OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI)
> -BDESC (OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)
> +BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)
>
>  /* SSSE3.  */
>  BDESC (OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_CONVERT)
> --- gcc/testsuite/gcc.target/i386/pr82483.c.jj  2017-10-09 12:40:28.182095322 +0200
> +++ gcc/testsuite/gcc.target/i386/pr82483.c     2017-10-09 12:58:45.150440839 +0200
> @@ -0,0 +1,42 @@
> +/* PR target/82483 */
> +/* { dg-do compile } */
> +/* { dg-options "-mssse3 -mno-mmx -Wno-psabi" } */
> +/* { dg-error "needs isa option" "" { target *-*-* } 0 } */
> +
> +#include <x86intrin.h>
> +
> +void f1 (__m64 x, __m64 y, char *z) { _mm_maskmove_si64 (x, y, z); }
> +int f2 (__m64 x) { return _mm_extract_pi16 (x, 1); }
> +__m64 f3 (__m64 x, int y) { return _mm_insert_pi16 (x, y, 1); }
> +__m64 f4 (__m128 x) { return _mm_cvtps_pi32 (x); }
> +__m64 f5 (__m128 x) { return _mm_cvttps_pi32 (x); }
> +__m128 f6 (__m128 x, __m64 y) { return _mm_cvtpi32_ps (x, y); }
> +__m64 f7 (__m64 x, __m64 y) { return _mm_avg_pu8 (x, y); }
> +__m64 f8 (__m64 x, __m64 y) { return _mm_avg_pu16 (x, y); }
> +__m64 f9 (__m64 x, __m64 y) { return _mm_mulhi_pu16 (x, y); }
> +__m64 f10 (__m64 x, __m64 y) { return _mm_max_pu8 (x, y); }
> +__m64 f11 (__m64 x, __m64 y) { return _mm_max_pi16 (x, y); }
> +__m64 f12 (__m64 x, __m64 y) { return _mm_min_pu8 (x, y); }
> +__m64 f13 (__m64 x, __m64 y) { return _mm_min_pi16 (x, y); }
> +__m64 f14 (__m64 x, __m64 y) { return _mm_sad_pu8 (x, y); }
> +int f15 (__m64 x) { return _mm_movemask_pi8 (x); }
> +__m64 f16 (__m64 x) { return _mm_shuffle_pi16 (x, 1); }
> +__m64 f17 (__m128d x) { return _mm_cvtpd_pi32 (x); }
> +__m64 f18 (__m128d x) { return _mm_cvttpd_pi32 (x); }
> +__m128d f19 (__m64 x) { return _mm_cvtpi32_pd (x); }
> +__m64 f20 (__m64 x, __m64 y) { return _mm_mul_su32 (x, y); }
> +__m64 f21 (__m64 x) { return _mm_abs_pi8 (x); }
> +__m64 f22 (__m64 x) { return _mm_abs_pi16 (x); }
> +__m64 f23 (__m64 x) { return _mm_abs_pi32 (x); }
> +__m64 f24 (__m64 x, __m64 y) { return _mm_hadd_pi16 (x, y); }
> +__m64 f25 (__m64 x, __m64 y) { return _mm_hadd_pi32 (x, y); }
> +__m64 f26 (__m64 x, __m64 y) { return _mm_hadds_pi16 (x, y); }
> +__m64 f27 (__m64 x, __m64 y) { return _mm_hsub_pi16 (x, y); }
> +__m64 f28 (__m64 x, __m64 y) { return _mm_hsub_pi32 (x, y); }
> +__m64 f29 (__m64 x, __m64 y) { return _mm_hsubs_pi16 (x, y); }
> +__m64 f30 (__m64 x, __m64 y) { return _mm_maddubs_pi16 (x, y); }
> +__m64 f31 (__m64 x, __m64 y) { return _mm_mulhrs_pi16 (x, y); }
> +__m64 f32 (__m64 x, __m64 y) { return _mm_shuffle_pi8 (x, y); }
> +__m64 f33 (__m64 x, __m64 y) { return _mm_sign_pi8 (x, y); }
> +__m64 f34 (__m64 x, __m64 y) { return _mm_sign_pi16 (x, y); }
> +__m64 f35 (__m64 x, __m64 y) { return _mm_sign_pi32 (x, y); }
>
>         Jakub

On Mon, Oct 09, 2017 at 09:28:58PM +0200, Uros Bizjak wrote:
> On Mon, Oct 9, 2017 at 9:16 PM, Jakub Jelinek <jakub@redhat.com> wrote:
> > Hi!
> >
> > The following builtins have {SSE,SSE2,SSSE3} CPUID, yet they have
> > MMX register operands (either input or output or both).
> > As -mno-mmx doesn't imply -mno-sse, we get ICEs on these though, because
> > with MMX disabled it is not possible to emit them.
> >
> > The following patch cheats and declares these builtins to require
> > both the MMX and {SSE,SSE2,SSSE3} ISA, making them unavailable in -mno-mmx
> > code, but I think it is the right thing to do, when somebody uses -mno-mmx,
> > the intent is usually not to have any instructions touching the MMX register
> > file and thus needing EMMS etc.
> >
> > Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?
> 
> Hm, I remember there was similar patch for PR79565 [1], which seems
> related. Does your patch also fix all builtins that HJ's patch touch?

Ah, I wasn't aware of that patch.  Will look in detail tomorrow.

> [1] https://gcc.gnu.org/ml/gcc-patches/2017-08/msg00751.html

Just quick analysis, while -mno-mmx doesn't imply -mno-sse (that is
right), it implies -mno-3dnow and -mno-3dnow implies -mno-3dnowa.
So all the spots that were changed from OPTION_MASK_ISA_3DNOW
to OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX or from
OPTION_MASK_ISA_3DNOW_A to OPTION_MASK_ISA_3DNOW_A | OPTION_MASK_ISA_MMX
were useless, we can do what we did before.
It is just OPTION_MASK_ISA_SSE or higher with OPTION_MASK_ISA_MMX that
is needed.
I have no idea why __builtin_ia32_sfence or __builtin_ia32_movntq were
changed.
Nor I understand why any sse.md changes are needed, then the builtins
aren't available, those insns shouldn't be synthetized out of thin air.
And the i386.c def_builtin change IMNSHO isn't needed either, it is
a compile time speed/memory optimization not to declare everything
unconditionally, and the way it works right now is that any of the enabled
ISAs enables the builtin, meaning that MMX enabled will mean those
35 will be declared, even when perhaps SSE isn't enabled, or for
SSE when MMX isn't enabled, but that isn't that big deal.

	Jakub

On 10/9/17, Jakub Jelinek <jakub@redhat.com> wrote:
> On Mon, Oct 09, 2017 at 09:28:58PM +0200, Uros Bizjak wrote:
>> On Mon, Oct 9, 2017 at 9:16 PM, Jakub Jelinek <jakub@redhat.com> wrote:
>> > Hi!
>> >
>> > The following builtins have {SSE,SSE2,SSSE3} CPUID, yet they have
>> > MMX register operands (either input or output or both).
>> > As -mno-mmx doesn't imply -mno-sse, we get ICEs on these though,
>> > because
>> > with MMX disabled it is not possible to emit them.
>> >
>> > The following patch cheats and declares these builtins to require
>> > both the MMX and {SSE,SSE2,SSSE3} ISA, making them unavailable in
>> > -mno-mmx
>> > code, but I think it is the right thing to do, when somebody uses
>> > -mno-mmx,
>> > the intent is usually not to have any instructions touching the MMX
>> > register
>> > file and thus needing EMMS etc.
>> >
>> > Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?
>>
>> Hm, I remember there was similar patch for PR79565 [1], which seems
>> related. Does your patch also fix all builtins that HJ's patch touch?
>
> Ah, I wasn't aware of that patch.  Will look in detail tomorrow.
>
>> [1] https://gcc.gnu.org/ml/gcc-patches/2017-08/msg00751.html
>
> Just quick analysis, while -mno-mmx doesn't imply -mno-sse (that is
> right), it implies -mno-3dnow and -mno-3dnow implies -mno-3dnowa.
> So all the spots that were changed from OPTION_MASK_ISA_3DNOW
> to OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX or from
> OPTION_MASK_ISA_3DNOW_A to OPTION_MASK_ISA_3DNOW_A | OPTION_MASK_ISA_MMX
> were useless, we can do what we did before.
> It is just OPTION_MASK_ISA_SSE or higher with OPTION_MASK_ISA_MMX that
> is needed.
> I have no idea why __builtin_ia32_sfence or __builtin_ia32_movntq were
> changed.
> Nor I understand why any sse.md changes are needed, then the builtins
> aren't available, those insns shouldn't be synthetized out of thin air.
> And the i386.c def_builtin change IMNSHO isn't needed either, it is
> a compile time speed/memory optimization not to declare everything
> unconditionally, and the way it works right now is that any of the enabled
> ISAs enables the builtin, meaning that MMX enabled will mean those
> 35 will be declared, even when perhaps SSE isn't enabled, or for
> SSE when MMX isn't enabled, but that isn't that big deal.
>
>

Please free feel to change it as long as there is no regression.

Thanks.