old mode 100644
new mode 100755
@@ -34,7 +34,7 @@ enum iomux_reg_addr {
IOMUXSW_MUX_CTL = IOMUXC_BASE_ADDR,
IOMUXSW_MUX_END = IOMUXC_BASE_ADDR + MUX_I_END,
IOMUXSW_PAD_CTL = IOMUXC_BASE_ADDR + PAD_I_START,
- IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR,
+ IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR + INPUT_CTL_START,
};
#define MUX_PIN_NUM_MAX (((MUX_I_END - MUX_I_START) >> 2) + 1)
@@ -44,20 +44,22 @@ static inline u32 get_mux_reg(iomux_pin_name_t pin)
{
u32 mux_reg = PIN_TO_IOMUX_MUX(pin);
- if (is_soc_rev(CHIP_REV_2_0) < 0) {
- /*
- * Fixup register address:
- * i.MX51 TO1 has offset with the register
- * which is define as TO2.
- */
- if ((pin == MX51_PIN_NANDF_RB5) ||
- (pin == MX51_PIN_NANDF_RB6) ||
- (pin == MX51_PIN_NANDF_RB7))
- ; /* Do nothing */
- else if (mux_reg >= 0x2FC)
- mux_reg += 8;
- else if (mux_reg >= 0x130)
- mux_reg += 0xC;
+ if (is_soc_type(MX_CPU_MX51)) {
+ if (is_soc_rev(CHIP_REV_2_0) < 0) {
+ /*
+ * Fixup register address:
+ * i.MX51 TO1 has offset with the register
+ * which is define as TO2.
+ */
+ if ((pin == MX51_PIN_NANDF_RB5) ||
+ (pin == MX51_PIN_NANDF_RB6) ||
+ (pin == MX51_PIN_NANDF_RB7))
+ ; /* Do nothing */
+ else if (mux_reg >= 0x2FC)
+ mux_reg += 8;
+ else if (mux_reg >= 0x130)
+ mux_reg += 0xC;
+ }
}
mux_reg += IOMUXSW_MUX_CTL;
return mux_reg;
@@ -68,28 +70,30 @@ static inline u32 get_pad_reg(iomux_pin_name_t pin)
{
u32 pad_reg = PIN_TO_IOMUX_PAD(pin);
- if (is_soc_rev(CHIP_REV_2_0) < 0) {
- /*
- * Fixup register address:
- * i.MX51 TO1 has offset with the register
- * which is define as TO2.
- */
- if ((pin == MX51_PIN_NANDF_RB5) ||
- (pin == MX51_PIN_NANDF_RB6) ||
- (pin == MX51_PIN_NANDF_RB7))
- ; /* Do nothing */
- else if (pad_reg == 0x4D0 - PAD_I_START)
- pad_reg += 0x4C;
- else if (pad_reg == 0x860 - PAD_I_START)
- pad_reg += 0x9C;
- else if (pad_reg >= 0x804 - PAD_I_START)
- pad_reg += 0xB0;
- else if (pad_reg >= 0x7FC - PAD_I_START)
- pad_reg += 0xB4;
- else if (pad_reg >= 0x4E4 - PAD_I_START)
- pad_reg += 0xCC;
- else
- pad_reg += 8;
+ if (is_soc_type(MX_CPU_MX51)) {
+ if (is_soc_rev(CHIP_REV_2_0) < 0) {
+ /*
+ * Fixup register address:
+ * i.MX51 TO1 has offset with the register
+ * which is define as TO2.
+ */
+ if ((pin == MX51_PIN_NANDF_RB5) ||
+ (pin == MX51_PIN_NANDF_RB6) ||
+ (pin == MX51_PIN_NANDF_RB7))
+ ; /* Do nothing */
+ else if (pad_reg == 0x4D0 - PAD_I_START)
+ pad_reg += 0x4C;
+ else if (pad_reg == 0x860 - PAD_I_START)
+ pad_reg += 0x9C;
+ else if (pad_reg >= 0x804 - PAD_I_START)
+ pad_reg += 0xB0;
+ else if (pad_reg >= 0x7FC - PAD_I_START)
+ pad_reg += 0xB4;
+ else if (pad_reg >= 0x4E4 - PAD_I_START)
+ pad_reg += 0xCC;
+ else
+ pad_reg += 8;
+ }
}
pad_reg += IOMUXSW_PAD_CTL;
return pad_reg;
@@ -98,10 +102,13 @@ static inline u32 get_pad_reg(iomux_pin_name_t pin)
/* Get the last iomux register address */
static inline u32 get_mux_end(void)
{
- if (is_soc_rev(CHIP_REV_2_0) < 0)
- return IOMUXC_BASE_ADDR + (0x3F8 - 4);
- else
- return IOMUXC_BASE_ADDR + (0x3F0 - 4);
+ if (is_soc_type(MX_CPU_MX51)) {
+ if (is_soc_rev(CHIP_REV_2_0) < 0)
+ return IOMUXC_BASE_ADDR + (0x3F8 - 4);
+ else
+ return IOMUXC_BASE_ADDR + (0x3F0 - 4);
+ }
+ return IOMUXSW_MUX_END;
}
/*
@@ -164,3 +171,16 @@ unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin)
u32 pad_reg = get_pad_reg(pin);
return readl(pad_reg);
}
+
+/*
+ * This function configures input path.
+ *
+ * @param input index of input select register
+ * @param config the binary value of elements
+ */
+void mxc_iomux_set_input(iomux_input_select_t input, u32 config)
+{
+ u32 reg = IOMUXSW_INPUT_CTL + (input << 2);
+
+ writel(config, reg);
+}
old mode 100644
new mode 100755
@@ -70,6 +70,7 @@
/* M4IF setup */
.macro init_m4if
+#ifdef CONFIG_MX51
/* VPU and IPU given higher priority (0x4)
* IPU accesses with ID=0x1 given highest priority (=0xA)
*/
@@ -87,27 +88,31 @@
ldr r1, =0x001901A3
str r1, [r0, #0x48]
+#endif
.endm /* init_m4if */
.macro setup_pll pll, freq
- ldr r2, =\pll
+ ldr r0, =\pll
ldr r1, =0x00001232
- str r1, [r2, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
+ str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
mov r1, #0x2
- str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
+ str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
- str r3, [r2, #PLL_DP_OP]
- str r3, [r2, #PLL_DP_HFS_OP]
+ ldr r1, W_DP_OP_\freq
+ str r1, [r0, #PLL_DP_OP]
+ str r1, [r0, #PLL_DP_HFS_OP]
- str r4, [r2, #PLL_DP_MFD]
- str r4, [r2, #PLL_DP_HFS_MFD]
+ ldr r1, W_DP_MFD_\freq
+ str r1, [r0, #PLL_DP_MFD]
+ str r1, [r0, #PLL_DP_HFS_MFD]
- str r5, [r2, #PLL_DP_MFN]
- str r5, [r2, #PLL_DP_HFS_MFN]
+ ldr r1, W_DP_MFN_\freq
+ str r1, [r0, #PLL_DP_MFN]
+ str r1, [r0, #PLL_DP_HFS_MFN]
ldr r1, =0x00001232
- str r1, [r2, #PLL_DP_CTL]
-1: ldr r1, [r2, #PLL_DP_CTL]
+ str r1, [r0, #PLL_DP_CTL]
+1: ldr r1, [r0, #PLL_DP_CTL]
ands r1, r1, #0x1
beq 1b
.endm
@@ -115,6 +120,7 @@
.macro init_clock
ldr r0, =CCM_BASE_ADDR
+#if defined(CONFIG_MX51)
/* Gate of clocks to the peripherals first */
ldr r1, =0x3FFFFFFF
str r1, [r0, #CLKCTL_CCGR0]
@@ -141,19 +147,16 @@
1: ldr r1, [r0, #CLKCTL_CDHIPR]
cmp r1, #0x0
bne 1b
+#endif
/* Switch ARM to step clock */
mov r1, #0x4
str r1, [r0, #CLKCTL_CCSR]
- mov r3, #DP_OP_800
- mov r4, #DP_MFD_800
- mov r5, #DP_MFN_800
- setup_pll PLL1_BASE_ADDR
- mov r3, #DP_OP_665
- mov r4, #DP_MFD_665
- mov r5, #DP_MFN_665
- setup_pll PLL3_BASE_ADDR
+ setup_pll PLL1_BASE_ADDR, 800
+
+#if defined(CONFIG_MX51)
+ setup_pll PLL3_BASE_ADDR, 665
/* Switch peripheral to PLL 3 */
ldr r0, =CCM_BASE_ADDR
@@ -162,10 +165,7 @@
str r1, [r0, #CLKCTL_CBCMR]
ldr r1, =0x13239145
str r1, [r0, #CLKCTL_CBCDR]
- mov r3, #DP_OP_665
- mov r4, #DP_MFD_665
- mov r5, #DP_MFN_665
- setup_pll PLL2_BASE_ADDR
+ setup_pll PLL2_BASE_ADDR, 665
/* Switch peripheral to PLL2 */
ldr r0, =CCM_BASE_ADDR
@@ -174,12 +174,8 @@
ldr r1, =0x000020C0
orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
str r1, [r0, #CLKCTL_CBCMR]
-
- mov r3, #DP_OP_216
- mov r4, #DP_MFD_216
- mov r5, #DP_MFN_216
- setup_pll PLL3_BASE_ADDR
-
+#endif
+ setup_pll PLL3_BASE_ADDR, 216
/* Set the platform clock dividers */
ldr r0, =ARM_BASE_ADDR
@@ -188,18 +184,24 @@
ldr r0, =CCM_BASE_ADDR
+#if defined(CONFIG_MX51)
/* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
ldr r1, =0x0
ldr r3, [r1, #ROM_SI_REV]
cmp r3, #0x10
movls r1, #0x1
movhi r1, #0
- str r1, [r0, #CLKCTL_CACRR]
+#else
+ /* Run at half speed, then full till we increase VDDGP */
+ mov r1, #1
+#endif
+ str r1, [r0, #CLKCTL_CACRR]
/* Switch ARM back to PLL 1 */
mov r1, #0
str r1, [r0, #CLKCTL_CCSR]
+#if defined(CONFIG_MX51)
/* setup the rest */
/* Use lp_apm (24MHz) source for perclk */
ldr r1, =0x000020C2
@@ -208,6 +210,7 @@
/* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
ldr r1, =CONFIG_SYS_CLKTL_CBCDR
str r1, [r0, #CLKCTL_CBCDR]
+#endif
/* Restore the default values in the Gate registers */
ldr r1, =0xFFFFFFFF
@@ -218,13 +221,23 @@
str r1, [r0, #CLKCTL_CCGR4]
str r1, [r0, #CLKCTL_CCGR5]
str r1, [r0, #CLKCTL_CCGR6]
+#if defined(CONFIG_MX53)
+ str r1, [r0, #CLKCTL_CCGR7]
+#endif
+#if defined(CONFIG_MX51)
/* Use PLL 2 for UART's, get 66.5MHz from it */
ldr r1, =0xA5A2A020
str r1, [r0, #CLKCTL_CSCMR1]
ldr r1, =0x00C30321
str r1, [r0, #CLKCTL_CSCDR1]
-
+#elif defined(CONFIG_MX53)
+ ldr r1, [r0, #CLKCTL_CSCDR1]
+ orr r1, r1, #0x3f
+ eor r1, r1, #0x3f
+ orr r1, r1, #0x21
+ str r1, [r0, #CLKCTL_CSCDR1]
+#endif
/* make sure divider effective */
1: ldr r1, [r0, #CLKCTL_CDHIPR]
cmp r1, #0x0
@@ -249,6 +262,7 @@
.globl lowlevel_init
lowlevel_init:
+#if defined(CONFIG_MX51)
ldr r0, =GPIO1_BASE_ADDR
ldr r1, [r0, #0x0]
orr r1, r1, #(1 << 23)
@@ -256,6 +270,7 @@ lowlevel_init:
ldr r1, [r0, #0x4]
orr r1, r1, #(1 << 23)
str r1, [r0, #0x4]
+#endif
init_l2cc
@@ -269,9 +284,12 @@ lowlevel_init:
mov pc,lr
/* Board level setting value */
-DDR_PERCHARGE_CMD: .word 0x04008008
-DDR_REFRESH_CMD: .word 0x00008010
-DDR_LMR1_W: .word 0x00338018
-DDR_LMR_CMD: .word 0xB2220000
-DDR_TIMING_W: .word 0xB02567A9
-DDR_MISC_W: .word 0x000A0104
+W_DP_OP_800: .word DP_OP_800
+W_DP_MFD_800: .word DP_MFD_800
+W_DP_MFN_800: .word DP_MFN_800
+W_DP_OP_665: .word DP_OP_665
+W_DP_MFD_665: .word DP_MFD_665
+W_DP_MFN_665: .word DP_MFN_665
+W_DP_OP_216: .word DP_OP_216
+W_DP_MFD_216: .word DP_MFD_216
+W_DP_MFN_216: .word DP_MFN_216
@@ -25,6 +25,7 @@
#include <common.h>
#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
#include <asm/arch/clock.h>
#include <asm/errno.h>
#include <asm/io.h>
@@ -34,7 +35,9 @@
#endif
#if defined(CONFIG_MX51)
-#define CPU_TYPE 0x51000
+#define CPU_TYPE MX_CPU_MX51
+#elif defined(CONFIG_MX53)
+#define CPU_TYPE MX_CPU_MX53
#else
#error "CPU_TYPE not defined"
#endif
old mode 100644
new mode 100755
@@ -20,38 +20,36 @@
* MA 02111-1307 USA
*/
-#ifndef __ASM_ARCH_MXC_MX51_H__
-#define __ASM_ARCH_MXC_MX51_H__
+#ifndef __ASM_ARCH_MX5_IMX_REGS_H__
+#define __ASM_ARCH_MX5_IMX_REGS_H__
-/*
- * IRAM
- */
+#if defined(CONFIG_MX51)
#define IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */
-#define IRAM_SIZE 0x00020000 /* 128 KB */
-/*
- * Graphics Memory of GPU
- */
-#define GPU_BASE_ADDR 0x20000000
-#define GPU_CTRL_BASE_ADDR 0x30000000
#define IPU_CTRL_BASE_ADDR 0x40000000
-/*
- * Debug
- */
-#define DEBUG_BASE_ADDR 0x60000000
-#define ETB_BASE_ADDR (DEBUG_BASE_ADDR + 0x00001000)
-#define ETM_BASE_ADDR (DEBUG_BASE_ADDR + 0x00002000)
-#define TPIU_BASE_ADDR (DEBUG_BASE_ADDR + 0x00003000)
-#define CTI0_BASE_ADDR (DEBUG_BASE_ADDR + 0x00004000)
-#define CTI1_BASE_ADDR (DEBUG_BASE_ADDR + 0x00005000)
-#define CTI2_BASE_ADDR (DEBUG_BASE_ADDR + 0x00006000)
-#define CTI3_BASE_ADDR (DEBUG_BASE_ADDR + 0x00007000)
-#define CORTEX_DBG_BASE_ADDR (DEBUG_BASE_ADDR + 0x00008000)
+#define SPBA0_BASE_ADDR 0x70000000
+#define AIPS1_BASE_ADDR 0x73F00000
+#define AIPS2_BASE_ADDR 0x83F00000
+#define CSD0_BASE_ADDR 0x90000000
+#define CSD1_BASE_ADDR 0xA0000000
+#define NFC_BASE_ADDR_AXI 0xCFFF0000
+#elif defined(CONFIG_MX53)
+#define IPU_CTRL_BASE_ADDR 0x18000000
+#define SPBA0_BASE_ADDR 0x50000000
+#define AIPS1_BASE_ADDR 0x53F00000
+#define AIPS2_BASE_ADDR 0x63F00000
+#define CSD0_BASE_ADDR 0x70000000
+#define CSD1_BASE_ADDR 0xB0000000
+#define NFC_BASE_ADDR_AXI 0xF7FF0000
+#define IRAM_BASE_ADDR 0xF8000000
+#else
+#error "CPU_TYPE not defined"
+#endif
+
+#define IRAM_SIZE 0x00020000 /* 128 KB */
/*
* SPBA global module enabled #0
*/
-#define SPBA0_BASE_ADDR 0x70000000
-
#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000)
#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000)
#define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000)
@@ -68,8 +66,6 @@
/*
* AIPS 1
*/
-#define AIPS1_BASE_ADDR 0x73F00000
-
#define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000)
#define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000)
#define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000)
@@ -94,8 +90,6 @@
/*
* AIPS 2
*/
-#define AIPS2_BASE_ADDR 0x83F00000
-
#define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000)
#define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000)
#define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000)
@@ -129,26 +123,7 @@
#define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000)
#define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000)
-#define TZIC_BASE_ADDR 0x8FFFC000
-
/*
- * Memory regions and CS
- */
-#define CSD0_BASE_ADDR 0x90000000
-#define CSD1_BASE_ADDR 0xA0000000
-#define CS0_BASE_ADDR 0xB0000000
-#define CS1_BASE_ADDR 0xB8000000
-#define CS2_BASE_ADDR 0xC0000000
-#define CS3_BASE_ADDR 0xC8000000
-#define CS4_BASE_ADDR 0xCC000000
-#define CS5_BASE_ADDR 0xCE000000
-
-/*
- * NFC
- */
-#define NFC_BASE_ADDR_AXI 0xCFFF0000 /* NAND flash AXI */
-
-/*!
* Number of GPIO port as defined in the IC Spec
*/
#define GPIO_PORT_NUM 4
@@ -277,4 +252,4 @@ struct src {
};
#endif /* __ASSEMBLER__*/
-#endif /* __ASM_ARCH_MXC_MX51_H__ */
+#endif /* __ASM_ARCH_MX5_IMX_REGS_H__ */
@@ -70,108 +70,6 @@ typedef enum iomux_pad_config {
PAD_CTL_DRV_VOT_HIGH = 0x1 << 13,/* High voltage mode */
} iomux_pad_config_t;
-/* various IOMUX input select register index */
-typedef enum iomux_input_select {
- MUX_IN_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0,
- MUX_IN_AUDMUX_P4_INPUT_DB_AMX_SELECT_I,
- MUX_IN_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P5_INPUT_RXFS_AMX_SELECT,
- MUX_IN_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT,
- MUX_IN_CCM_IPP_DI_CLK_SELECT_INPUT,
- /* TO2 */
- MUX_IN_CCM_IPP_DI1_CLK_SELECT_INPUT,
- MUX_IN_CCM_PLL1_BYPASS_CLK_SELECT_INPUT,
- MUX_IN_CCM_PLL2_BYPASS_CLK_SELECT_INPUT,
- MUX_IN_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT,
- MUX_IN_CSPI_IPP_IND_MISO_SELECT_INPUT,
- MUX_IN_CSPI_IPP_IND_MOSI_SELECT_INPUT,
- MUX_IN_CSPI_IPP_IND_SS_B_1_SELECT_INPUT,
- MUX_IN_CSPI_IPP_IND_SS_B_2_SELECT_INPUT,
- MUX_IN_CSPI_IPP_IND_SS_B_3_SELECT_INPUT,
- MUX_IN_DPLLIP1_L1T_TOG_EN_SELECT_INPUT,
- /* TO2 */
- MUX_IN_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT,
- MUX_IN_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT,
- MUX_IN_EMI_IPP_IND_RDY_INT_SELECT_INPUT,
- MUX_IN_ESDHC3_IPP_DAT0_IN_SELECT_INPUT,
- MUX_IN_ESDHC3_IPP_DAT1_IN_SELECT_INPUT,
- MUX_IN_ESDHC3_IPP_DAT2_IN_SELECT_INPUT,
- MUX_IN_ESDHC3_IPP_DAT3_IN_SELECT_INPUT,
- MUX_IN_FEC_FEC_COL_SELECT_INPUT,
- MUX_IN_FEC_FEC_CRS_SELECT_INPUT,
- MUX_IN_FEC_FEC_MDI_SELECT_INPUT,
- MUX_IN_FEC_FEC_RDATA_0_SELECT_INPUT,
- MUX_IN_FEC_FEC_RDATA_1_SELECT_INPUT,
- MUX_IN_FEC_FEC_RDATA_2_SELECT_INPUT,
- MUX_IN_FEC_FEC_RDATA_3_SELECT_INPUT,
- MUX_IN_FEC_FEC_RX_CLK_SELECT_INPUT,
- MUX_IN_FEC_FEC_RX_DV_SELECT_INPUT,
- MUX_IN_FEC_FEC_RX_ER_SELECT_INPUT,
- MUX_IN_FEC_FEC_TX_CLK_SELECT_INPUT,
- MUX_IN_GPIO3_IPP_IND_G_IN_1_SELECT_INPUT,
- MUX_IN_GPIO3_IPP_IND_G_IN_2_SELECT_INPUT,
- MUX_IN_GPIO3_IPP_IND_G_IN_3_SELECT_INPUT,
- MUX_IN_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT,
- MUX_IN_GPIO3_IPP_IND_G_IN_5_SELECT_INPUT,
- MUX_IN_GPIO3_IPP_IND_G_IN_6_SELECT_INPUT,
- MUX_IN_GPIO3_IPP_IND_G_IN_7_SELECT_INPUT,
- MUX_IN_GPIO3_IPP_IND_G_IN_8_SELECT_INPUT,
- /* TO2 */
- MUX_IN_GPIO3_IPP_IND_G_IN_12_SELECT_INPUT,
- MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS1_DATA_EN_SELECT_INPUT,
- MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS2_DATA_EN_SELECT_INPUT,
- /* TO2 */
- MUX_IN_HSC_MIPI_MIX_PAR_VSYNC_SELECT_INPUT,
- /* TO2 */
- MUX_IN_HSC_MIPI_MIX_PAR_DI_WAIT_SELECT_INPUT,
- MUX_IN_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT,
- MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT,
- MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT,
- MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT,
- MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT,
-
- MUX_IN_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT,
-
- MUX_IN_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT,
-
- MUX_IN_KPP_IPP_IND_COL_6_SELECT_INPUT,
- MUX_IN_KPP_IPP_IND_COL_7_SELECT_INPUT,
- MUX_IN_KPP_IPP_IND_ROW_4_SELECT_INPUT,
- MUX_IN_KPP_IPP_IND_ROW_5_SELECT_INPUT,
- MUX_IN_KPP_IPP_IND_ROW_6_SELECT_INPUT,
- MUX_IN_KPP_IPP_IND_ROW_7_SELECT_INPUT,
- MUX_IN_UART1_IPP_UART_RTS_B_SELECT_INPUT,
- MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT,
- MUX_IN_UART2_IPP_UART_RTS_B_SELECT_INPUT,
- MUX_IN_UART2_IPP_UART_RXD_MUX_SELECT_INPUT,
- MUX_IN_UART3_IPP_UART_RTS_B_SELECT_INPUT,
- MUX_IN_UART3_IPP_UART_RXD_MUX_SELECT_INPUT,
- MUX_IN_USBOH3_IPP_IND_UH3_CLK_SELECT_INPUT,
- MUX_IN_USBOH3_IPP_IND_UH3_DATA_0_SELECT_INPUT,
- MUX_IN_USBOH3_IPP_IND_UH3_DATA_1_SELECT_INPUT,
- MUX_IN_USBOH3_IPP_IND_UH3_DATA_2_SELECT_INPUT,
- MUX_IN_USBOH3_IPP_IND_UH3_DATA_3_SELECT_INPUT,
- MUX_IN_USBOH3_IPP_IND_UH3_DATA_4_SELECT_INPUT,
- MUX_IN_USBOH3_IPP_IND_UH3_DATA_5_SELECT_INPUT,
- MUX_IN_USBOH3_IPP_IND_UH3_DATA_6_SELECT_INPUT,
- MUX_IN_USBOH3_IPP_IND_UH3_DATA_7_SELECT_INPUT,
- MUX_IN_USBOH3_IPP_IND_UH3_DIR_SELECT_INPUT,
- MUX_IN_USBOH3_IPP_IND_UH3_NXT_SELECT_INPUT,
- MUX_IN_USBOH3_IPP_IND_UH3_STP_SELECT_INPUT,
- MUX_INPUT_NUM_MUX,
-} iomux_input_select_t;
-
/* various IOMUX input functions */
typedef enum iomux_input_config {
INPUT_CTL_PATH0 = 0x0,
old mode 100644
new mode 100755
@@ -86,12 +86,22 @@
#define PIN_TO_PAD_MASK ((1 << (GPIO_I - PAD_I)) - 1)
#define PIN_TO_ALT_GPIO_MASK ((1 << (MUX_IO_I - GPIO_I)) - 1)
-#define NON_MUX_I PIN_TO_MUX_MASK
+#define NON_MUX_I PIN_TO_MUX_MASK
+#define NON_PAD_I PIN_TO_PAD_MASK
+
+#if defined(CONFIG_MX51)
#define MUX_I_START 0x001C
#define PAD_I_START 0x3F0
#define INPUT_CTL_START 0x8C4
-#define INPUT_CTL_START_TO1 0x928
#define MUX_I_END (PAD_I_START - 4)
+#elif defined(CONFIG_MX53)
+#define MUX_I_START 0x0020
+#define PAD_I_START 0x348
+#define INPUT_CTL_START 0x730
+#define MUX_I_END (PAD_I_START - 4)
+#else
+#error "CPU_TYPE not defined"
+#endif
#define _MXC_BUILD_PIN(gp, gi, ga, mi, pi) \
(((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \
@@ -115,7 +125,7 @@
* "sw_pad_ctl & sw_mux_ctl details" of the MX51 IC Spec. Each enumerated
* value is constructed based on the rules described above.
*/
-enum iomux_pins {
+enum {
MX51_PIN_EIM_DA0 = _MXC_BUILD_NON_GPIO_PIN(0x1C, 0x7A8),
MX51_PIN_EIM_DA1 = _MXC_BUILD_NON_GPIO_PIN(0x20, 0x7A8),
MX51_PIN_EIM_DA2 = _MXC_BUILD_NON_GPIO_PIN(0x24, 0x7A8),
@@ -414,5 +424,458 @@ enum iomux_pins {
MX51_PIN_CTL_DRAM_DQM3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4E0),
};
+enum {
+ MX53_PIN_GPIO_19 = _MXC_BUILD_GPIO_PIN(3, 5, 1, 0x20, 0x348),
+ MX53_PIN_KEY_COL0 = _MXC_BUILD_GPIO_PIN(3, 6, 1, 0x24, 0x34C),
+ MX53_PIN_KEY_ROW0 = _MXC_BUILD_GPIO_PIN(3, 7, 1, 0x28, 0x350),
+ MX53_PIN_KEY_COL1 = _MXC_BUILD_GPIO_PIN(3, 8, 1, 0x2C, 0x354),
+ MX53_PIN_KEY_ROW1 = _MXC_BUILD_GPIO_PIN(3, 9, 1, 0x30, 0x358),
+ MX53_PIN_KEY_COL2 = _MXC_BUILD_GPIO_PIN(3, 10, 1, 0x34, 0x35C),
+ MX53_PIN_KEY_ROW2 = _MXC_BUILD_GPIO_PIN(3, 11, 1, 0x38, 0x360),
+ MX53_PIN_KEY_COL3 = _MXC_BUILD_GPIO_PIN(3, 12, 1, 0x3C, 0x364),
+ MX53_PIN_KEY_ROW3 = _MXC_BUILD_GPIO_PIN(3, 13, 1, 0x40, 0x368),
+ MX53_PIN_KEY_COL4 = _MXC_BUILD_GPIO_PIN(3, 14, 1, 0x44, 0x36C),
+ MX53_PIN_KEY_ROW4 = _MXC_BUILD_GPIO_PIN(3, 15, 1, 0x48, 0x370),
+ MX53_PIN_NVCC_KEYPAD = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x374),
+ MX53_PIN_DI0_DISP_CLK = _MXC_BUILD_GPIO_PIN(3, 16, 1, 0x4C, 0x378),
+ MX53_PIN_DI0_PIN15 = _MXC_BUILD_GPIO_PIN(3, 17, 1, 0x50, 0x37C),
+ MX53_PIN_DI0_PIN2 = _MXC_BUILD_GPIO_PIN(3, 18, 1, 0x54, 0x380),
+ MX53_PIN_DI0_PIN3 = _MXC_BUILD_GPIO_PIN(3, 19, 1, 0x58, 0x384),
+ MX53_PIN_DI0_PIN4 = _MXC_BUILD_GPIO_PIN(3, 20, 1, 0x5C, 0x388),
+ MX53_PIN_DISP0_DAT0 = _MXC_BUILD_GPIO_PIN(3, 21, 1, 0x60, 0x38C),
+ MX53_PIN_DISP0_DAT1 = _MXC_BUILD_GPIO_PIN(3, 22, 1, 0x64, 0x390),
+ MX53_PIN_DISP0_DAT2 = _MXC_BUILD_GPIO_PIN(3, 23, 1, 0x68, 0x394),
+ MX53_PIN_DISP0_DAT3 = _MXC_BUILD_GPIO_PIN(3, 24, 1, 0x6C, 0x398),
+ MX53_PIN_DISP0_DAT4 = _MXC_BUILD_GPIO_PIN(3, 25, 1, 0x70, 0x39C),
+ MX53_PIN_DISP0_DAT5 = _MXC_BUILD_GPIO_PIN(3, 26, 1, 0x74, 0x3A0),
+ MX53_PIN_DISP0_DAT6 = _MXC_BUILD_GPIO_PIN(3, 27, 1, 0x78, 0x3A4),
+ MX53_PIN_DISP0_DAT7 = _MXC_BUILD_GPIO_PIN(3, 28, 1, 0x7C, 0x3A8),
+ MX53_PIN_DISP0_DAT8 = _MXC_BUILD_GPIO_PIN(3, 29, 1, 0x80, 0x3AC),
+ MX53_PIN_DISP0_DAT9 = _MXC_BUILD_GPIO_PIN(3, 30, 1, 0x84, 0x3B0),
+ MX53_PIN_DISP0_DAT10 = _MXC_BUILD_GPIO_PIN(3, 31, 1, 0x88, 0x3B4),
+ MX53_PIN_DISP0_DAT11 = _MXC_BUILD_GPIO_PIN(4, 5, 1, 0x8C, 0x3B8),
+ MX53_PIN_DISP0_DAT12 = _MXC_BUILD_GPIO_PIN(4, 6, 1, 0x90, 0x3BC),
+ MX53_PIN_DISP0_DAT13 = _MXC_BUILD_GPIO_PIN(4, 7, 1, 0x94, 0x3C0),
+ MX53_PIN_DISP0_DAT14 = _MXC_BUILD_GPIO_PIN(4, 8, 1, 0x98, 0x3C4),
+ MX53_PIN_DISP0_DAT15 = _MXC_BUILD_GPIO_PIN(4, 9, 1, 0x9C, 0x3C8),
+ MX53_PIN_DISP0_DAT16 = _MXC_BUILD_GPIO_PIN(4, 10, 1, 0xA0, 0x3CC),
+ MX53_PIN_DISP0_DAT17 = _MXC_BUILD_GPIO_PIN(4, 11, 1, 0xA4, 0x3D0),
+ MX53_PIN_DISP0_DAT18 = _MXC_BUILD_GPIO_PIN(4, 12, 1, 0xA8, 0x3D4),
+ MX53_PIN_DISP0_DAT19 = _MXC_BUILD_GPIO_PIN(4, 13, 1, 0xAC, 0x3D8),
+ MX53_PIN_DISP0_DAT20 = _MXC_BUILD_GPIO_PIN(4, 14, 1, 0xB0, 0x3DC),
+ MX53_PIN_DISP0_DAT21 = _MXC_BUILD_GPIO_PIN(4, 15, 1, 0xB4, 0x3E0),
+ MX53_PIN_DISP0_DAT22 = _MXC_BUILD_GPIO_PIN(4, 16, 1, 0xB8, 0x3E4),
+ MX53_PIN_DISP0_DAT23 = _MXC_BUILD_GPIO_PIN(4, 17, 1, 0xBC, 0x3E8),
+ MX53_PIN_CSI0_PIXCLK = _MXC_BUILD_GPIO_PIN(4, 18, 1, 0xC0, 0x3EC),
+ MX53_PIN_CSI0_MCLK = _MXC_BUILD_GPIO_PIN(4, 19, 1, 0xC4, 0x3F0),
+ MX53_PIN_CSI0_DATA_EN = _MXC_BUILD_GPIO_PIN(4, 20, 1, 0xC8, 0x3F4),
+ MX53_PIN_CSI0_VSYNC = _MXC_BUILD_GPIO_PIN(4, 21, 1, 0xCC, 0x3F8),
+ MX53_PIN_CSI0_D4 = _MXC_BUILD_GPIO_PIN(4, 22, 1, 0xD0, 0x3FC),
+ MX53_PIN_CSI0_D5 = _MXC_BUILD_GPIO_PIN(4, 23, 1, 0xD4, 0x400),
+ MX53_PIN_CSI0_D6 = _MXC_BUILD_GPIO_PIN(4, 24, 1, 0xD8, 0x404),
+ MX53_PIN_CSI0_D7 = _MXC_BUILD_GPIO_PIN(4, 25, 1, 0xDC, 0x408),
+ MX53_PIN_CSI0_D8 = _MXC_BUILD_GPIO_PIN(4, 26, 1, 0xE0, 0x40C),
+ MX53_PIN_CSI0_D9 = _MXC_BUILD_GPIO_PIN(4, 27, 1, 0xE4, 0x410),
+ MX53_PIN_CSI0_D10 = _MXC_BUILD_GPIO_PIN(4, 28, 1, 0xE8, 0x414),
+ MX53_PIN_CSI0_D11 = _MXC_BUILD_GPIO_PIN(4, 29, 1, 0xEC, 0x418),
+ MX53_PIN_CSI0_D12 = _MXC_BUILD_GPIO_PIN(4, 30, 1, 0xF0, 0x41C),
+ MX53_PIN_CSI0_D13 = _MXC_BUILD_GPIO_PIN(4, 31, 1, 0xF4, 0x420),
+ MX53_PIN_CSI0_D14 = _MXC_BUILD_GPIO_PIN(5, 0, 1, 0xF8, 0x424),
+ MX53_PIN_CSI0_D15 = _MXC_BUILD_GPIO_PIN(5, 1, 1, 0xFC, 0x428),
+ MX53_PIN_CSI0_D16 = _MXC_BUILD_GPIO_PIN(5, 2, 1, 0x100, 0x42C),
+ MX53_PIN_CSI0_D17 = _MXC_BUILD_GPIO_PIN(5, 3, 1, 0x104, 0x430),
+ MX53_PIN_CSI0_D18 = _MXC_BUILD_GPIO_PIN(5, 4, 1, 0x108, 0x434),
+ MX53_PIN_CSI0_D19 = _MXC_BUILD_GPIO_PIN(5, 5, 1, 0x10C, 0x438),
+ MX53_PIN_NVCC_CSI0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x43C),
+ MX53_PIN_JTAG_TMS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x440),
+ MX53_PIN_JTAG_MOD = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x444),
+ MX53_PIN_JTAG_TRSTB = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x448),
+ MX53_PIN_JTAG_TDI = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x44C),
+ MX53_PIN_JTAG_TCK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x450),
+ MX53_PIN_JTAG_TDO = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x454),
+ MX53_PIN_EIM_A25 = _MXC_BUILD_GPIO_PIN(4, 2, 1, 0x110, 0x458),
+ MX53_PIN_EIM_EB2 = _MXC_BUILD_GPIO_PIN(1, 30, 1, 0x114, 0x45C),
+ MX53_PIN_EIM_D16 = _MXC_BUILD_GPIO_PIN(2, 16, 1, 0x118, 0x460),
+ MX53_PIN_EIM_D17 = _MXC_BUILD_GPIO_PIN(2, 17, 1, 0x11C, 0x464),
+ MX53_PIN_EIM_D18 = _MXC_BUILD_GPIO_PIN(2, 18, 1, 0x120, 0x468),
+ MX53_PIN_EIM_D19 = _MXC_BUILD_GPIO_PIN(2, 19, 1, 0x124, 0x46C),
+ MX53_PIN_EIM_D20 = _MXC_BUILD_GPIO_PIN(2, 20, 1, 0x128, 0x470),
+ MX53_PIN_EIM_D21 = _MXC_BUILD_GPIO_PIN(2, 21, 1, 0x12C, 0x474),
+ MX53_PIN_EIM_D22 = _MXC_BUILD_GPIO_PIN(2, 22, 1, 0x130, 0x478),
+ MX53_PIN_EIM_D23 = _MXC_BUILD_GPIO_PIN(2, 23, 1, 0x134, 0x47C),
+ MX53_PIN_EIM_EB3 = _MXC_BUILD_GPIO_PIN(1, 31, 1, 0x138, 0x480),
+ MX53_PIN_EIM_D24 = _MXC_BUILD_GPIO_PIN(2, 24, 1, 0x13C, 0x484),
+ MX53_PIN_EIM_D25 = _MXC_BUILD_GPIO_PIN(2, 25, 1, 0x140, 0x488),
+ MX53_PIN_EIM_D26 = _MXC_BUILD_GPIO_PIN(2, 26, 1, 0x144, 0x48C),
+ MX53_PIN_EIM_D27 = _MXC_BUILD_GPIO_PIN(2, 27, 1, 0x148, 0x490),
+ MX53_PIN_EIM_D28 = _MXC_BUILD_GPIO_PIN(2, 28, 1, 0x14C, 0x494),
+ MX53_PIN_EIM_D29 = _MXC_BUILD_GPIO_PIN(2, 29, 1, 0x150, 0x498),
+ MX53_PIN_EIM_D30 = _MXC_BUILD_GPIO_PIN(2, 30, 1, 0x154, 0x49C),
+ MX53_PIN_EIM_D31 = _MXC_BUILD_GPIO_PIN(2, 31, 1, 0x158, 0x4A0),
+ MX53_PIN_NVCC_EIM1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4A4),
+ MX53_PIN_EIM_A24 = _MXC_BUILD_GPIO_PIN(4, 4, 1, 0x15C, 0x4A8),
+ MX53_PIN_EIM_A23 = _MXC_BUILD_GPIO_PIN(5, 6, 1, 0x160, 0x4AC),
+ MX53_PIN_EIM_A22 = _MXC_BUILD_GPIO_PIN(1, 16, 1, 0x164, 0x4B0),
+ MX53_PIN_EIM_A21 = _MXC_BUILD_GPIO_PIN(1, 17, 1, 0x168, 0x4B4),
+ MX53_PIN_EIM_A20 = _MXC_BUILD_GPIO_PIN(1, 18, 1, 0x16C, 0x4B8),
+ MX53_PIN_EIM_A19 = _MXC_BUILD_GPIO_PIN(1, 19, 1, 0x170, 0x4BC),
+ MX53_PIN_EIM_A18 = _MXC_BUILD_GPIO_PIN(1, 20, 1, 0x174, 0x4C0),
+ MX53_PIN_EIM_A17 = _MXC_BUILD_GPIO_PIN(1, 21, 1, 0x178, 0x4C4),
+ MX53_PIN_EIM_A16 = _MXC_BUILD_GPIO_PIN(1, 22, 1, 0x17C, 0x4C8),
+ MX53_PIN_EIM_CS0 = _MXC_BUILD_GPIO_PIN(1, 23, 1, 0x180, 0x4CC),
+ MX53_PIN_EIM_CS1 = _MXC_BUILD_GPIO_PIN(1, 24, 1, 0x184, 0x4D0),
+ MX53_PIN_EIM_OE = _MXC_BUILD_GPIO_PIN(1, 25, 1, 0x188, 0x4D4),
+ MX53_PIN_EIM_RW = _MXC_BUILD_GPIO_PIN(1, 26, 1, 0x18C, 0x4D8),
+ MX53_PIN_EIM_LBA = _MXC_BUILD_GPIO_PIN(1, 27, 1, 0x190, 0x4DC),
+ MX53_PIN_NVCC_EIM4 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4E0),
+ MX53_PIN_EIM_EB0 = _MXC_BUILD_GPIO_PIN(1, 28, 1, 0x194, 0x4E4),
+ MX53_PIN_EIM_EB1 = _MXC_BUILD_GPIO_PIN(1, 29, 1, 0x198, 0x4E8),
+ MX53_PIN_EIM_DA0 = _MXC_BUILD_GPIO_PIN(2, 0, 1, 0x19C, 0x4EC),
+ MX53_PIN_EIM_DA1 = _MXC_BUILD_GPIO_PIN(2, 1, 1, 0x1A0, 0x4F0),
+ MX53_PIN_EIM_DA2 = _MXC_BUILD_GPIO_PIN(2, 2, 1, 0x1A4, 0x4F4),
+ MX53_PIN_EIM_DA3 = _MXC_BUILD_GPIO_PIN(2, 3, 1, 0x1A8, 0x4F8),
+ MX53_PIN_EIM_DA4 = _MXC_BUILD_GPIO_PIN(2, 4, 1, 0x1AC, 0x4FC),
+ MX53_PIN_EIM_DA5 = _MXC_BUILD_GPIO_PIN(2, 5, 1, 0x1B0, 0x500),
+ MX53_PIN_EIM_DA6 = _MXC_BUILD_GPIO_PIN(2, 6, 1, 0x1B4, 0x504),
+ MX53_PIN_EIM_DA7 = _MXC_BUILD_GPIO_PIN(2, 7, 1, 0x1B8, 0x508),
+ MX53_PIN_EIM_DA8 = _MXC_BUILD_GPIO_PIN(2, 8, 1, 0x1BC, 0x50C),
+ MX53_PIN_EIM_DA9 = _MXC_BUILD_GPIO_PIN(2, 9, 1, 0x1C0, 0x510),
+ MX53_PIN_EIM_DA10 = _MXC_BUILD_GPIO_PIN(2, 10, 1, 0x1C4, 0x514),
+ MX53_PIN_EIM_DA11 = _MXC_BUILD_GPIO_PIN(2, 11, 1, 0x1C8, 0x518),
+ MX53_PIN_EIM_DA12 = _MXC_BUILD_GPIO_PIN(2, 12, 1, 0x1CC, 0x51C),
+ MX53_PIN_EIM_DA13 = _MXC_BUILD_GPIO_PIN(2, 13, 1, 0x1D0, 0x520),
+ MX53_PIN_EIM_DA14 = _MXC_BUILD_GPIO_PIN(2, 14, 1, 0x1D4, 0x524),
+ MX53_PIN_EIM_DA15 = _MXC_BUILD_GPIO_PIN(2, 15, 1, 0x1D8, 0x528),
+ MX53_PIN_NANDF_WE_B = _MXC_BUILD_GPIO_PIN(5, 12, 1, 0x1DC, 0x52C),
+ MX53_PIN_NANDF_RE_B = _MXC_BUILD_GPIO_PIN(5, 13, 1, 0x1E0, 0x530),
+ MX53_PIN_EIM_WAIT = _MXC_BUILD_GPIO_PIN(4, 0, 1, 0x1E4, 0x534),
+ MX53_PIN_EIM_BCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x538),
+ MX53_PIN_NVCC_EIM7 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x53C),
+ MX53_PIN_LVDS1_TX3_P = _MXC_BUILD_GPIO_PIN(5, 22, 0, 0x1EC, NON_PAD_I),
+ MX53_PIN_LVDS1_TX2_P = _MXC_BUILD_GPIO_PIN(5, 24, 0, 0x1F0, NON_PAD_I),
+ MX53_PIN_LVDS1_CLK_P = _MXC_BUILD_GPIO_PIN(5, 26, 0, 0x1F4, NON_PAD_I),
+ MX53_PIN_LVDS1_TX1_P = _MXC_BUILD_GPIO_PIN(5, 28, 0, 0x1F8, NON_PAD_I),
+ MX53_PIN_LVDS1_TX0_P = _MXC_BUILD_GPIO_PIN(5, 30, 0, 0x1FC, NON_PAD_I),
+ MX53_PIN_LVDS0_TX3_P = _MXC_BUILD_GPIO_PIN(6, 22, 0, 0x200, NON_PAD_I),
+ MX53_PIN_LVDS0_CLK_P = _MXC_BUILD_GPIO_PIN(6, 24, 0, 0x204, NON_PAD_I),
+ MX53_PIN_LVDS0_TX2_P = _MXC_BUILD_GPIO_PIN(6, 26, 0, 0x208, NON_PAD_I),
+ MX53_PIN_LVDS0_TX1_P = _MXC_BUILD_GPIO_PIN(6, 28, 0, 0x20C, NON_PAD_I),
+ MX53_PIN_LVDS0_TX0_P = _MXC_BUILD_GPIO_PIN(6, 30, 0, 0x210, NON_PAD_I),
+ MX53_PIN_GPIO_10 = _MXC_BUILD_GPIO_PIN(3, 0, 0, 0x214, 0x540),
+ MX53_PIN_GPIO_11 = _MXC_BUILD_GPIO_PIN(3, 1, 0, 0x218, 0x544),
+ MX53_PIN_GPIO_12 = _MXC_BUILD_GPIO_PIN(3, 2, 0, 0x21C, 0x548),
+ MX53_PIN_GPIO_13 = _MXC_BUILD_GPIO_PIN(3, 3, 0, 0x220, 0x54C),
+ MX53_PIN_GPIO_14 = _MXC_BUILD_GPIO_PIN(3, 4, 0, 0x224, 0x550),
+ MX53_PIN_DRAM_DQM3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x554),
+ MX53_PIN_DRAM_SDQS3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x558),
+ MX53_PIN_DRAM_SDCKE1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x55C),
+ MX53_PIN_DRAM_DQM2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x560),
+ MX53_PIN_DRAM_SDODT1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x564),
+ MX53_PIN_DRAM_SDQS2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x568),
+ MX53_PIN_DRAM_RESET = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x56C),
+ MX53_PIN_DRAM_SDCLK1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x570),
+ MX53_PIN_DRAM_CAS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x574),
+ MX53_PIN_DRAM_SDCLK0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x578),
+ MX53_PIN_DRAM_SDQS0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x57C),
+ MX53_PIN_DRAM_SDODT0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x580),
+ MX53_PIN_DRAM_DQM0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x584),
+ MX53_PIN_DRAM_RAS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x588),
+ MX53_PIN_DRAM_SDCKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x58C),
+ MX53_PIN_DRAM_SDQS1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x590),
+ MX53_PIN_DRAM_DQM1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x594),
+ MX53_PIN_PMIC_ON_REQ = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x598),
+ MX53_PIN_PMIC_STBY_REQ = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x59C),
+ MX53_PIN_NANDF_CLE = _MXC_BUILD_GPIO_PIN(5, 7, 1, 0x228, 0x5A0),
+ MX53_PIN_NANDF_ALE = _MXC_BUILD_GPIO_PIN(5, 8 , 1, 0x22C, 0x5A4),
+ MX53_PIN_NANDF_WP_B = _MXC_BUILD_GPIO_PIN(5, 9, 1, 0x230, 0x5A8),
+ MX53_PIN_NANDF_RB0 = _MXC_BUILD_GPIO_PIN(5, 10, 1, 0x234, 0x5AC),
+ MX53_PIN_NANDF_CS0 = _MXC_BUILD_GPIO_PIN(5, 11, 1, 0x238, 0x5B0),
+ MX53_PIN_NANDF_CS1 = _MXC_BUILD_GPIO_PIN(5, 14, 1, 0x23C, 0x5B4),
+ MX53_PIN_NANDF_CS2 = _MXC_BUILD_GPIO_PIN(5, 15, 1, 0x240, 0x5B8),
+ MX53_PIN_NANDF_CS3 = _MXC_BUILD_GPIO_PIN(5, 16, 1, 0x244, 0x5BC),
+ MX53_PIN_NVCC_NANDF = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5C0),
+ MX53_PIN_FEC_MDIO = _MXC_BUILD_GPIO_PIN(0, 22, 1, 0x248, 0x5C4),
+ MX53_PIN_FEC_REF_CLK = _MXC_BUILD_GPIO_PIN(0, 23, 1, 0x24C, 0x5C8),
+ MX53_PIN_FEC_RX_ER = _MXC_BUILD_GPIO_PIN(0, 24, 1, 0x250, 0x5CC),
+ MX53_PIN_FEC_CRS_DV = _MXC_BUILD_GPIO_PIN(0, 25, 1, 0x254, 0x5D0),
+ MX53_PIN_FEC_RXD1 = _MXC_BUILD_GPIO_PIN(0, 26, 1, 0x258, 0x5D4),
+ MX53_PIN_FEC_RXD0 = _MXC_BUILD_GPIO_PIN(0, 27, 1, 0x25C, 0x5D8),
+ MX53_PIN_FEC_TX_EN = _MXC_BUILD_GPIO_PIN(0, 28, 1, 0x260, 0x5DC),
+ MX53_PIN_FEC_TXD1 = _MXC_BUILD_GPIO_PIN(0, 29, 1, 0x264, 0x5E0),
+ MX53_PIN_FEC_TXD0 = _MXC_BUILD_GPIO_PIN(0, 30, 1, 0x268, 0x5E4),
+ MX53_PIN_FEC_MDC = _MXC_BUILD_GPIO_PIN(0, 31, 1, 0x26C, 0x5E8),
+ MX53_PIN_NVCC_FEC = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5EC),
+ MX53_PIN_ATA_DIOW = _MXC_BUILD_GPIO_PIN(5, 17, 1, 0x270, 0x5F0),
+ MX53_PIN_ATA_DMACK = _MXC_BUILD_GPIO_PIN(5, 18, 1, 0x274, 0x5F4),
+ MX53_PIN_ATA_DMARQ = _MXC_BUILD_GPIO_PIN(6, 0, 1, 0x278, 0x5F8),
+ MX53_PIN_ATA_BUFFER_EN = _MXC_BUILD_GPIO_PIN(6, 1, 1, 0x27C, 0x5FC),
+ MX53_PIN_ATA_INTRQ = _MXC_BUILD_GPIO_PIN(6, 2, 1, 0x280, 0x600),
+ MX53_PIN_ATA_DIOR = _MXC_BUILD_GPIO_PIN(6, 3, 1, 0x284, 0x604),
+ MX53_PIN_ATA_RESET_B = _MXC_BUILD_GPIO_PIN(6, 4, 1, 0x288, 0x608),
+ MX53_PIN_ATA_IORDY = _MXC_BUILD_GPIO_PIN(6, 5, 1, 0x28C, 0x60C),
+ MX53_PIN_ATA_DA_0 = _MXC_BUILD_GPIO_PIN(6, 6, 1, 0x290, 0x610),
+ MX53_PIN_ATA_DA_1 = _MXC_BUILD_GPIO_PIN(6, 7, 1, 0x294, 0x614),
+ MX53_PIN_ATA_DA_2 = _MXC_BUILD_GPIO_PIN(6, 8, 1, 0x298, 0x618),
+ MX53_PIN_ATA_CS_0 = _MXC_BUILD_GPIO_PIN(6, 9, 1, 0x29C, 0x61C),
+ MX53_PIN_ATA_CS_1 = _MXC_BUILD_GPIO_PIN(6, 10, 1, 0x2A0, 0x620),
+ MX53_PIN_NVCC_ATA2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x624),
+ MX53_PIN_ATA_DATA0 = _MXC_BUILD_GPIO_PIN(1, 0, 1, 0x2A4, 0x628),
+ MX53_PIN_ATA_DATA1 = _MXC_BUILD_GPIO_PIN(1, 1, 1, 0x2A8, 0x62C),
+ MX53_PIN_ATA_DATA2 = _MXC_BUILD_GPIO_PIN(1, 2, 1, 0x2AC, 0x630),
+ MX53_PIN_ATA_DATA3 = _MXC_BUILD_GPIO_PIN(1, 3, 1, 0x2B0, 0x634),
+ MX53_PIN_ATA_DATA4 = _MXC_BUILD_GPIO_PIN(1, 4, 1, 0x2B4, 0x638),
+ MX53_PIN_ATA_DATA5 = _MXC_BUILD_GPIO_PIN(1, 5, 1, 0x2B8, 0x63C),
+ MX53_PIN_ATA_DATA6 = _MXC_BUILD_GPIO_PIN(1, 6, 1, 0x2BC, 0x640),
+ MX53_PIN_ATA_DATA7 = _MXC_BUILD_GPIO_PIN(1, 7, 1, 0x2C0, 0x644),
+ MX53_PIN_ATA_DATA8 = _MXC_BUILD_GPIO_PIN(1, 8, 1, 0x2C4, 0x648),
+ MX53_PIN_ATA_DATA9 = _MXC_BUILD_GPIO_PIN(1, 9, 1, 0x2C8, 0x64C),
+ MX53_PIN_ATA_DATA10 = _MXC_BUILD_GPIO_PIN(1, 10, 1, 0x2CC, 0x650),
+ MX53_PIN_ATA_DATA11 = _MXC_BUILD_GPIO_PIN(1, 11, 1, 0x2D0, 0x654),
+ MX53_PIN_ATA_DATA12 = _MXC_BUILD_GPIO_PIN(1, 12, 1, 0x2D4, 0x658),
+ MX53_PIN_ATA_DATA13 = _MXC_BUILD_GPIO_PIN(1, 13, 1, 0x2D8, 0x65C),
+ MX53_PIN_ATA_DATA14 = _MXC_BUILD_GPIO_PIN(1, 14, 1, 0x2DC, 0x660),
+ MX53_PIN_ATA_DATA15 = _MXC_BUILD_GPIO_PIN(1, 15, 1, 0x2E0, 0x664),
+ MX53_PIN_NVCC_ATA0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x668),
+ MX53_PIN_SD1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 16, 1, 0x2E4, 0x66C),
+ MX53_PIN_SD1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 17, 1, 0x2E8, 0x670),
+ MX53_PIN_SD1_CMD = _MXC_BUILD_GPIO_PIN(0, 18, 1, 0x2EC, 0x674),
+ MX53_PIN_SD1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 19, 1, 0x2F0, 0x678),
+ MX53_PIN_SD1_CLK = _MXC_BUILD_GPIO_PIN(0, 20, 1, 0x2F4, 0x67C),
+ MX53_PIN_SD1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 21, 1, 0x2F8, 0x680),
+ MX53_PIN_NVCC_SD1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x684),
+ MX53_PIN_SD2_CLK = _MXC_BUILD_GPIO_PIN(0, 10, 1, 0x2FC, 0x688),
+ MX53_PIN_SD2_CMD = _MXC_BUILD_GPIO_PIN(0, 11, 1, 0x300, 0x68C),
+ MX53_PIN_SD2_DATA3 = _MXC_BUILD_GPIO_PIN(0, 12, 1, 0x304, 0x690),
+ MX53_PIN_SD2_DATA2 = _MXC_BUILD_GPIO_PIN(0, 13, 1, 0x308, 0x694),
+ MX53_PIN_SD2_DATA1 = _MXC_BUILD_GPIO_PIN(0, 14, 1, 0x30C, 0x698),
+ MX53_PIN_SD2_DATA0 = _MXC_BUILD_GPIO_PIN(0, 15, 1, 0x310, 0x69C),
+ MX53_PIN_NVCC_SD2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6A0),
+ MX53_PIN_GPIO_0 = _MXC_BUILD_GPIO_PIN(0, 0, 1, 0x314, 0x6A4),
+ MX53_PIN_GPIO_1 = _MXC_BUILD_GPIO_PIN(0, 1, 1, 0x318, 0x6A8),
+ MX53_PIN_GPIO_9 = _MXC_BUILD_GPIO_PIN(0, 9, 1, 0x31C, 0x6AC),
+ MX53_PIN_GPIO_3 = _MXC_BUILD_GPIO_PIN(0, 3, 1, 0x320, 0x6B0),
+ MX53_PIN_GPIO_6 = _MXC_BUILD_GPIO_PIN(0, 6, 1, 0x324, 0x6B4),
+ MX53_PIN_GPIO_2 = _MXC_BUILD_GPIO_PIN(0, 2, 1, 0x328, 0x6B8),
+ MX53_PIN_GPIO_4 = _MXC_BUILD_GPIO_PIN(0, 4, 1, 0x32C, 0x6BC),
+ MX53_PIN_GPIO_5 = _MXC_BUILD_GPIO_PIN(0, 5, 1, 0x330, 0x6C0),
+ MX53_PIN_GPIO_7 = _MXC_BUILD_GPIO_PIN(0, 7, 1, 0x334, 0x6C4),
+ MX53_PIN_GPIO_8 = _MXC_BUILD_GPIO_PIN(0, 8, 1, 0x338, 0x6C8),
+ MX53_PIN_GPIO_16 = _MXC_BUILD_GPIO_PIN(6, 11, 1, 0x33C, 0x6CC),
+ MX53_PIN_GPIO_17 = _MXC_BUILD_GPIO_PIN(6, 12, 1, 0x340, 0x6D0),
+ MX53_PIN_GPIO_18 = _MXC_BUILD_GPIO_PIN(6, 13, 1, 0x344, 0x6D4),
+ MX53_PIN_NVCC_GPIO = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6D8),
+ MX53_PIN_POR_B = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6DC),
+ MX53_PIN_BOOT_MODE1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6E0),
+ MX53_PIN_RESET_IN_B = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6E4),
+ MX53_PIN_BOOT_MODE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6E8),
+ MX53_PIN_TEST_MODE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6EC),
+ MX53_PIN_GRP_ADDDS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6F0),
+ MX53_PIN_GRP_DDRMODE_CTL = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6F4),
+ MX53_PIN_GRP_DDRPKE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6FC),
+ MX53_PIN_GRP_DDRPK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x708),
+ MX53_PIN_GRP_TERM_CTL3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x70C),
+ MX53_PIN_GRP_DDRHYS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x710),
+ MX53_PIN_GRP_DDRMODE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x714),
+ MX53_PIN_GRP_B0DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x718),
+ MX53_PIN_GRP_B1DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x71C),
+ MX53_PIN_GRP_CTLDS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x720),
+ MX53_PIN_GRP_DDR_TYPE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x724),
+ MX53_PIN_GRP_B2DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x728),
+ MX53_PIN_GRP_B3DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x72C),
+};
+/* various IOMUX input select register index */
+typedef enum iomux_input_select {
+ MX51_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0,
+ MX51_AUDMUX_P4_INPUT_DB_AMX_SELECT_I,
+ MX51_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT,
+ MX51_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT,
+ MX51_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT,
+ MX51_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT,
+ MX51_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT,
+ MX51_AUDMUX_P5_INPUT_RXFS_AMX_SELECT,
+ MX51_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT,
+ MX51_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT,
+ MX51_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT,
+ MX51_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT,
+ MX51_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT,
+ MX51_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT,
+ MX51_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT,
+ MX51_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT,
+ MX51_CCM_IPP_DI_CLK_SELECT_INPUT,
+ /* TO2 */
+ MX51_CCM_IPP_DI1_CLK_SELECT_INPUT,
+ MX51_CCM_PLL1_BYPASS_CLK_SELECT_INPUT,
+ MX51_CCM_PLL2_BYPASS_CLK_SELECT_INPUT,
+ MX51_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT,
+ MX51_CSPI_IPP_IND_MISO_SELECT_INPUT,
+ MX51_CSPI_IPP_IND_MOSI_SELECT_INPUT,
+ MX51_CSPI_IPP_IND_SS_B_1_SELECT_INPUT,
+ MX51_CSPI_IPP_IND_SS_B_2_SELECT_INPUT,
+ MX51_CSPI_IPP_IND_SS_B_3_SELECT_INPUT,
+ MX51_DPLLIP1_L1T_TOG_EN_SELECT_INPUT,
+ /* TO2 */
+ MX51_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT,
+ MX51_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT,
+ MX51_EMI_IPP_IND_RDY_INT_SELECT_INPUT,
+ MX51_ESDHC3_IPP_DAT0_IN_SELECT_INPUT,
+ MX51_ESDHC3_IPP_DAT1_IN_SELECT_INPUT,
+ MX51_ESDHC3_IPP_DAT2_IN_SELECT_INPUT,
+ MX51_ESDHC3_IPP_DAT3_IN_SELECT_INPUT,
+ MX51_FEC_FEC_COL_SELECT_INPUT,
+ MX51_FEC_FEC_CRS_SELECT_INPUT,
+ MX51_FEC_FEC_MDI_SELECT_INPUT,
+ MX51_FEC_FEC_RDATA_0_SELECT_INPUT,
+ MX51_FEC_FEC_RDATA_1_SELECT_INPUT,
+ MX51_FEC_FEC_RDATA_2_SELECT_INPUT,
+ MX51_FEC_FEC_RDATA_3_SELECT_INPUT,
+ MX51_FEC_FEC_RX_CLK_SELECT_INPUT,
+ MX51_FEC_FEC_RX_DV_SELECT_INPUT,
+ MX51_FEC_FEC_RX_ER_SELECT_INPUT,
+ MX51_FEC_FEC_TX_CLK_SELECT_INPUT,
+ MX51_GPIO3_IPP_IND_G_IN_1_SELECT_INPUT,
+ MX51_GPIO3_IPP_IND_G_IN_2_SELECT_INPUT,
+ MX51_GPIO3_IPP_IND_G_IN_3_SELECT_INPUT,
+ MX51_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT,
+ MX51_GPIO3_IPP_IND_G_IN_5_SELECT_INPUT,
+ MX51_GPIO3_IPP_IND_G_IN_6_SELECT_INPUT,
+ MX51_GPIO3_IPP_IND_G_IN_7_SELECT_INPUT,
+ MX51_GPIO3_IPP_IND_G_IN_8_SELECT_INPUT,
+ /* TO2 */
+ MX51_GPIO3_IPP_IND_G_IN_12_SELECT_INPUT,
+ MX51_HSC_MIPI_MIX_IPP_IND_SENS1_DATA_EN_SELECT_INPUT,
+ MX51_HSC_MIPI_MIX_IPP_IND_SENS2_DATA_EN_SELECT_INPUT,
+ /* TO2 */
+ MX51_HSC_MIPI_MIX_PAR_VSYNC_SELECT_INPUT,
+ /* TO2 */
+ MX51_HSC_MIPI_MIX_PAR_DI_WAIT_SELECT_INPUT,
+ MX51_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT,
+ MX51_I2C1_IPP_SCL_IN_SELECT_INPUT,
+ MX51_I2C1_IPP_SDA_IN_SELECT_INPUT,
+ MX51_I2C2_IPP_SCL_IN_SELECT_INPUT,
+ MX51_I2C2_IPP_SDA_IN_SELECT_INPUT,
+ MX51_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT,
+ MX51_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT,
+ MX51_KPP_IPP_IND_COL_6_SELECT_INPUT,
+ MX51_KPP_IPP_IND_COL_7_SELECT_INPUT,
+ MX51_KPP_IPP_IND_ROW_4_SELECT_INPUT,
+ MX51_KPP_IPP_IND_ROW_5_SELECT_INPUT,
+ MX51_KPP_IPP_IND_ROW_6_SELECT_INPUT,
+ MX51_KPP_IPP_IND_ROW_7_SELECT_INPUT,
+ MX51_UART1_IPP_UART_RTS_B_SELECT_INPUT,
+ MX51_UART1_IPP_UART_RXD_MUX_SELECT_INPUT,
+ MX51_UART2_IPP_UART_RTS_B_SELECT_INPUT,
+ MX51_UART2_IPP_UART_RXD_MUX_SELECT_INPUT,
+ MX51_UART3_IPP_UART_RTS_B_SELECT_INPUT,
+ MX51_UART3_IPP_UART_RXD_MUX_SELECT_INPUT,
+ MX51_USBOH3_IPP_IND_UH3_CLK_SELECT_INPUT,
+ MX51_USBOH3_IPP_IND_UH3_DATA_0_SELECT_INPUT,
+ MX51_USBOH3_IPP_IND_UH3_DATA_1_SELECT_INPUT,
+ MX51_USBOH3_IPP_IND_UH3_DATA_2_SELECT_INPUT,
+ MX51_USBOH3_IPP_IND_UH3_DATA_3_SELECT_INPUT,
+ MX51_USBOH3_IPP_IND_UH3_DATA_4_SELECT_INPUT,
+ MX51_USBOH3_IPP_IND_UH3_DATA_5_SELECT_INPUT,
+ MX51_USBOH3_IPP_IND_UH3_DATA_6_SELECT_INPUT,
+ MX51_USBOH3_IPP_IND_UH3_DATA_7_SELECT_INPUT,
+ MX51_USBOH3_IPP_IND_UH3_DIR_SELECT_INPUT,
+ MX51_USBOH3_IPP_IND_UH3_NXT_SELECT_INPUT,
+ MX51_USBOH3_IPP_IND_UH3_STP_SELECT_INPUT,
+ MX51PUT_NUM_MUX,
+ /* MX53 */
+ MX53_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0,
+ MX53_AUDMUX_P4_INPUT_DB_AMX_SELECT_I,
+ MX53_AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT,
+ MX53_AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT,
+ MX53_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT,
+ MX53_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT,
+ MX53_AUDMUX_P5_INPUT_DA_AMX_SELECT_I,
+ MX53_AUDMUX_P5_INPUT_DB_AMX_SELECT_I,
+ MX53_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT,
+ MX53_AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT,
+ MX53_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT,
+ MX53_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT,
+ MX53_CAN1_IPP_IND_CANRX_SELECT_INPUT, /*0x760*/
+ MX53_CAN2_IPP_IND_CANRX_SELECT_INPUT,
+ MX53_CCM_IPP_ASRC_EXT_SELECT_INPUT,
+ MX53_CCM_IPP_DI1_CLK_SELECT_INPUT,
+ MX53_CCM_PLL1_BYPASS_CLK_SELECT_INPUT,
+ MX53_CCM_PLL2_BYPASS_CLK_SELECT_INPUT,
+ MX53_CCM_PLL3_BYPASS_CLK_SELECT_INPUT,
+ MX53_CCM_PLL4_BYPASS_CLK_SELECT_INPUT,
+ MX53_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT, /*0x780*/
+ MX53_CSPI_IPP_IND_MISO_SELECT_INPUT,
+ MX53_CSPI_IPP_IND_MOSI_SELECT_INPUT,
+ MX53_CSPI_IPP_IND_SS_B_1_SELECT_INPUT,
+ MX53_CSPI_IPP_IND_SS_B_2_SELECT_INPUT,
+ MX53_CSPI_IPP_IND_SS_B_3_SELECT_INPUT,
+ MX53_CSPI_IPP_IND_SS_B_4_SELECT_INPUT,
+ MX53_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT,
+ MX53_ECSPI1_IPP_IND_MISO_SELECT_INPUT,
+ MX53_ECSPI1_IPP_IND_MOSI_SELECT_INPUT,
+ MX53_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT,
+ MX53_ECSPI1_IPP_IND_SS_B_2_SELECT_INPUT,
+ MX53_ECSPI1_IPP_IND_SS_B_3_SELECT_INPUT, /*0x7B0*/
+ MX53_ECSPI1_IPP_IND_SS_B_4_SELECT_INPUT,
+ MX53_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT,
+ MX53_ECSPI2_IPP_IND_MISO_SELECT_INPUT,
+ MX53_ECSPI2_IPP_IND_MOSI_SELECT_INPUT,
+ MX53_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT,
+ MX53_ECSPI2_IPP_IND_SS_B_2_SELECT_INPUT,
+ MX53_ESAI1_IPP_IND_FSR_SELECT_INPUT,
+ MX53_ESAI1_IPP_IND_FST_SELECT_INPUT,
+ MX53_ESAI1_IPP_IND_HCKR_SELECT_INPUT,
+ MX53_ESAI1_IPP_IND_HCKT_SELECT_INPUT,
+ MX53_ESAI1_IPP_IND_SCKR_SELECT_INPUT,
+ MX53_ESAI1_IPP_IND_SCKT_SELECT_INPUT, /*0x7E0*/
+ MX53_ESAI1_IPP_IND_SDO0_SELECT_INPUT,
+ MX53_ESAI1_IPP_IND_SDO1_SELECT_INPUT,
+ MX53_ESAI1_IPP_IND_SDO2_SDI3_SELECT_INPUT,
+ MX53_ESAI1_IPP_IND_SDO3_SDI2_SELECT_INPUT,
+ MX53_ESAI1_IPP_IND_SDO4_SDI1_SELECT_INPUT,
+ MX53_ESAI1_IPP_IND_SDO5_SDI0_SELECT_INPUT,
+ MX53_ESDHC1_IPP_WP_ON_SELECT_INPUT,
+ MX53_FEC_FEC_COL_SELECT_INPUT, /*0x800*/
+ MX53_FEC_FEC_MDI_SELECT_INPUT,
+ MX53_FEC_FEC_RX_CLK_SELECT_INPUT,
+ MX53_FIRI_IPP_IND_RXD_SELECT_INPUT,
+ MX53_GPC_PMIC_RDY_SELECT_INPUT,
+ MX53_I2C1_IPP_SCL_IN_SELECT_INPUT,
+ MX53_I2C1_IPP_SDA_IN_SELECT_INPUT,
+ MX53_I2C2_IPP_SCL_IN_SELECT_INPUT,
+ MX53_I2C2_IPP_SDA_IN_SELECT_INPUT,
+ MX53_I2C3_IPP_SCL_IN_SELECT_INPUT,
+ MX53_I2C3_IPP_SDA_IN_SELECT_INPUT,
+ MX53_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT,
+ MX53_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT,
+ MX53_IPU_IPP_IND_SENS1_DATA_EN_SELECT_INPUT,
+ MX53_IPU_IPP_IND_SENS1_HSYNC_SELECT_INPUT,
+ MX53_IPU_IPP_IND_SENS1_VSYNC_SELECT_INPUT,
+ MX53_KPP_IPP_IND_COL_5_SELECT_INPUT, /*0x840*/
+ MX53_KPP_IPP_IND_COL_6_SELECT_INPUT,
+ MX53_KPP_IPP_IND_COL_7_SELECT_INPUT,
+ MX53_KPP_IPP_IND_ROW_5_SELECT_INPUT,
+ MX53_KPP_IPP_IND_ROW_6_SELECT_INPUT,
+ MX53_KPP_IPP_IND_ROW_7_SELECT_INPUT,
+ MX53_MLB_MLBCLK_IN_SELECT_INPUT,
+ MX53_MLB_MLBDAT_IN_SELECT_INPUT,
+ MX53_MLB_MLBSIG_IN_SELECT_INPUT,
+ MX53_OWIRE_BATTERY_LINE_IN_SELECT_INPUT,
+ MX53_SDMA_EVENTS_14_SELECT_INPUT,
+ MX53_SDMA_EVENTS_15_SELECT_INPUT,
+ MX53_SPDIF_SPDIF_IN1_SELECT_INPUT, /*0x870*/
+ MX53_UART1_IPP_UART_RTS_B_SELECT_INPUT,
+ MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT,
+ MX53_UART2_IPP_UART_RTS_B_SELECT_INPUT,
+ MX53_UART2_IPP_UART_RXD_MUX_SELECT_INPUT,
+ MX53_UART3_IPP_UART_RTS_B_SELECT_INPUT,
+ MX53_UART3_IPP_UART_RXD_MUX_SELECT_INPUT,
+ MX53_UART4_IPP_UART_RTS_B_SELECT_INPUT,
+ MX53_UART4_IPP_UART_RXD_MUX_SELECT_INPUT,
+ MX53_UART5_IPP_UART_RTS_B_SELECT_INPUT,
+ MX53_UART5_IPP_UART_RXD_MUX_SELECT_INPUT,
+ MX53_USBOH3_IPP_IND_OTG_OC_SELECT_INPUT,
+ MX53_USBOH3_IPP_IND_UH1_OC_SELECT_INPUT,
+ MX53_USBOH3_IPP_IND_UH2_OC_SELECT_INPUT,
+} iomux_input_select_t;
+
#endif /* __ASSEMBLY__ */
#endif /* __ASM_ARCH_MX5_MX5X_PINS_H__ */
old mode 100644
new mode 100755
@@ -24,8 +24,13 @@
#ifndef _SYS_PROTO_H_
#define _SYS_PROTO_H_
-u32 get_cpu_rev(void);
+#define MX_CPU_MX51 0x51000
+#define MX_CPU_MX53 0x53000
+
#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev)
+#define is_soc_type(rev)((get_cpu_rev() & 0xFF000) == rev)
+
+u32 get_cpu_rev(void);
void sdelay(unsigned long);
#endif
@@ -24,8 +24,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#include <asm/arch/imx-regs.h>
-
/* High Level Configuration Options */
#define CONFIG_MX51 /* in a mx51 */
@@ -37,6 +35,7 @@
#define CONFIG_L2_OFF
+#include <asm/arch/imx-regs.h>
/*
* Disabled for now due to build problems under Debian and a significant
* increase in the final file size: 144260 vs. 109536 Bytes.
Add initial support for mx53 with the following change, - Add the iomux support and the pin definition, - Add the regs definition, clean up some unused def from mx51, - Add the low level init support, make use the freq input of setup_pll macro This patch has been tested on MX51 Babbage 3.0 Signed-off-by: Jason Liu <r64343@freescale.com> --- arch/arm/cpu/armv7/mx5/iomux.c | 102 ++++--- arch/arm/cpu/armv7/mx5/lowlevel_init.S | 92 ++++--- arch/arm/cpu/armv7/mx5/soc.c | 5 +- arch/arm/include/asm/arch-mx5/imx-regs.h | 73 ++--- arch/arm/include/asm/arch-mx5/iomux.h | 102 ------- arch/arm/include/asm/arch-mx5/mx5x_pins.h | 469 ++++++++++++++++++++++++++++- arch/arm/include/asm/arch-mx5/sys_proto.h | 7 +- include/configs/mx51evk.h | 3 +- 8 files changed, 617 insertions(+), 236 deletions(-)