[rs6000] testcase coverage for vector load builtins

diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-char.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-char.c
new file mode 100644
index 0000000..f9ef3e0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-char.c
@@ -0,0 +1,71 @@ 
+/* Verify that overloaded built-ins for vec_ld* with char
+   inputs produce the right code.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2" } */
+
+#include <altivec.h>
+
+vector signed char
+testld_sc_vsc (long long ll1, vector signed char vsc2)
+{
+  return vec_ld (ll1, &vsc2);
+}
+
+vector signed char
+testld_sc_sc (long long ll1, signed char sc)
+{
+  return vec_ld (ll1, &sc);
+}
+
+vector unsigned char
+testld_uc_vuc (long long ll1, vector unsigned char vuc2)
+{
+  return vec_ld (ll1, &vuc2);
+}
+
+vector unsigned char
+testld_uc_uc (long long ll1, unsigned char uc)
+{
+  return vec_ld (ll1, &uc);
+}
+
+vector bool char
+testld_bc_vbc (long long ll1, vector bool char vbc2)
+{
+  return vec_ld (ll1, &vbc2);
+}
+
+vector signed char
+testld_cst_vsc (vector signed char vsc2)
+{
+  return vec_ld (16, &vsc2);
+}
+
+vector signed char
+testld_cst_sc (signed char sc)
+{
+  return vec_ld (32, &sc);
+}
+
+vector unsigned char
+testld_cst_vuc (vector unsigned char vuc2)
+{
+  return vec_ld (48, &vuc2);
+}
+
+vector unsigned char
+testld_cst_uc (unsigned char uc)
+{
+  return vec_ld (64, &uc);
+}
+
+vector bool char
+testld_cst_vbc (vector bool char vbc2)
+{
+  return vec_ld (80, &vbc2);
+}
+
+/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvd2x\M|\mlxvw4x\M}
10 } } */
+
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-double.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-double.c
new file mode 100644
index 0000000..9c6fbb2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-double.c
@@ -0,0 +1,22 @@ 
+/* Verify that overloaded built-ins for vec_ld with 
+   double inputs produce the right code.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-mvsx -O2" } */
+
+#include <altivec.h>
+
+vector double
+testld_ll_vd (long long ll1, vector double vd)
+{
+  return vec_ld (ll1, &vd);
+}
+
+vector double
+testld_cst_vd (long long ll1, vector double vd)
+{
+  return vec_ld (16, &vd);
+}
+
+/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvd2x\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-float.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-float.c
new file mode 100644
index 0000000..eca847a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-float.c
@@ -0,0 +1,37 @@ 
+/* Verify that overloaded built-ins for vec_ld with float
+   inputs produce the right code.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2" } */
+
+#include <altivec.h>
+
+vector float
+testld_ll_vf (long long ll1, vector float vf2)
+{
+  return vec_ld (ll1, &vf2);
+}
+
+vector float
+testld_ll_f (long long ll1, float f2)
+{
+  return vec_ld (ll1, &f2);
+}
+
+vector float
+testld_cst_vf (vector float vf2)
+{
+  return vec_ld (16, &vf2);
+}
+
+vector float
+testld_cst_f (float f2)
+{
+  return vec_ld (16, &f2);
+}
+
+// lvx - generated by ll_vf and ll_f
+// lxvd2x - generated by cst_vf and cst_f
+/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvd2x\M} 4 } } */
+
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-int.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-int.c
new file mode 100644
index 0000000..5dc6df6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-int.c
@@ -0,0 +1,71 @@ 
+/* Verify that overloaded built-ins for vec_ld* with int
+   inputs produce the right code.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2" } */
+
+#include <altivec.h>
+
+vector signed int
+testld_vsi_vsi (long long ll1, vector signed int vsi2)
+{
+  return vec_ld (ll1, &vsi2);
+}
+
+vector signed int
+testld_vsi_si (long long ll1, signed int si)
+{
+  return vec_ld (ll1, &si);
+}
+
+vector unsigned int
+testld_vui_vui (long long ll1, vector unsigned int vui2)
+{
+  return vec_ld (ll1, &vui2);
+}
+
+vector unsigned int
+testld_vui_ui (long long ll1, unsigned int ui)
+{
+  return vec_ld (ll1, &ui);
+}
+
+vector bool int
+testld_vbi_vbi (long long ll1, vector bool int vbi2)
+{
+  return vec_ld (ll1, &vbi2);
+}
+
+vector signed int
+testld_cst_vsi (vector signed int vsi2)
+{
+  return vec_ld (16, &vsi2);
+}
+
+vector signed int
+testld_cst_si (signed int si)
+{
+  return vec_ld (32, &si);
+}
+
+vector unsigned int
+testld_cst_vui (vector unsigned int vui2)
+{
+  return vec_ld (48, &vui2);
+}
+
+vector unsigned int
+testld_cst_ui (unsigned int ui)
+{
+  return vec_ld (64, &ui);
+}
+
+vector bool int
+testld_cst_vbi (vector bool int vbi2)
+{
+  return vec_ld (80, &vbi2);
+}
+
+/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvd2x\M|\mlxvw4x\M}
10 } } */
+
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-longlong.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-longlong.c
new file mode 100644
index 0000000..37941af
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-longlong.c
@@ -0,0 +1,47 @@ 
+/* Verify that overloaded built-ins for vec_ld* with long long
+   inputs produce the right code.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mpower8-vector -O2" } */
+
+#include <altivec.h>
+
+vector signed long long
+testld_vsl_vsl (long long ll1, vector signed long vsl2)
+{
+  return vec_ld (ll1, &vsl2);
+}
+
+vector unsigned long long
+testld_vul_vul (long long ll1, vector unsigned long vul2)
+{
+  return vec_ld (ll1, &vul2);
+}
+
+vector bool long long
+testld_vbl_vbl (long long ll1, vector bool long vbl2)
+{
+  return vec_ld (ll1, &vbl2);
+}
+
+vector signed long long
+testld_cst_vsl (vector signed long vsl2)
+{
+  return vec_ld (16, &vsl2);
+}
+
+vector unsigned long long
+testld_cst_vul (vector unsigned long vul2)
+{
+  return vec_ld (32, &vul2);
+}
+
+vector bool long long
+testld_cst_vbl (vector bool long vbl2)
+{
+  return vec_ld (48, &vbl2);
+}
+
+/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvd2x\M} 6 } } */
+
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-short.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-short.c
new file mode 100644
index 0000000..5e42844
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-short.c
@@ -0,0 +1,71 @@ 
+/* Verify that overloaded built-ins for vec_ld* with short
+   inputs produce the right code.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2" } */
+
+#include <altivec.h>
+
+vector signed short
+testld_vss_vss (long long ll1, vector signed short vss2)
+{
+  return vec_ld (ll1, &vss2);
+}
+
+vector signed short
+testld_vss_ss (long long ll1, signed short ss)
+{
+  return vec_ld (ll1, &ss);
+}
+
+vector unsigned short
+testld_vus_vus (long long ll1, vector unsigned short vus2)
+{
+  return vec_ld (ll1, &vus2);
+}
+
+vector unsigned short
+testld_vus_us (long long ll1, unsigned short us)
+{
+  return vec_ld (ll1, &us);
+}
+
+vector bool short
+testld_vbs_vbs (long long ll1, vector bool short vbs2)
+{
+  return vec_ld (ll1, &vbs2);
+}
+
+vector signed short
+testld_cst_vss (vector signed short vss2)
+{
+  return vec_ld (16, &vss2);
+}
+
+vector signed short
+testld_cst_ss (signed short ss)
+{
+  return vec_ld (32, &ss);
+}
+
+vector unsigned short
+testld_cst_vus (vector unsigned short vus2)
+{
+  return vec_ld (48, &vus2);
+}
+
+vector unsigned short
+testld_cst_us (unsigned short us)
+{
+  return vec_ld (64, &us);
+}
+
+vector bool short
+testld_cst_vbs (vector bool short vbs2)
+{
+  return vec_ld (80, &vbs2);
+}
+
+/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvd2x\M|\mlxvw4x\M}
10 } } */